Tiempo Secure
France
Tiempo Secure is an independent company headquartered near Grenoble, France, founded in 2007, with customers in Europe, North America and Asia, and specialized in the development of IP cores and embedded software for securing connected devices.
The company offers a wide range of hardware secure enclaves, i.e., Secure Elements, the latest version integrating a secure RISC-V processor (TESIC family). These Secure Elements are ready to be integrated into “System-on-Chip” (SoC) products and guarantee their maximum security against all state-of-the-art cyberattacks.
Tiempo Secure guarantees the Common Criteria EAL5+ certification of any SoC integrating a TESIC Secure Element and can offer complete solutions for many security applications: authentication on networks with integrated SIM (iSIM/iUICC), embedded payment (EMVCo), government or private identification, Web authentication (FIDO 2), smart car access, communication with autonomous vehicles (V2X HSM).
Services
CC EAL5+ certification of customer chips
Our security experts handle the Common Criteria (CC) EAL5+ PP0084 / PP0117 or similar (e.g., EMVCo or PP V2X HSM) security certification of customer chips integrating our TESIC Secure Element cores. This work includes the writing of the CC-compliant documentation, the preparation of the customer chip samples and boards for the evaluation, the support of the ITSEF labs during customer chip evaluation and certification, and the interactions with the national cybersecurity agency to obtain the CC certificate.
Secure personalization of customer chips
Our expert developers configure HSM servers to perform customer chip personalization at production/test phase and during customer chip/external flash firmware programming. Tiempo Secure can also host and operate HSM servers at Tiempo Secure CC certified site to perform these personalization services.
IP Cores
TESIC RISC-V CC EAL5+ Secure Element
Targeted designs are SoCs that require a security enclave highly protected against side-channel attacks and perturbation/fault attacks, and that execute secure software such as iSIM/iUICC, EMVCo payment, FIDO2 Web authentication, V2X HSM protocol and/or other security routines for the SoC, including secure boot, secure OTA firmware update, secure storage and secure debug.
TESIC RISC-V includes a secure 32-bit RISC-V microprocessor core, secure cryptographic hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. Memory sizes, cryptographic accelerators and interfaces can be customized according to customer requirements.
TESIC RISC-V supports any non-volatile memory (NVM) architecture, including embedded flash and MRAM, and the use of any external flash chip. It implements a CC EAL5+ PP0084 / PP0117 compliant security protocol for the encrypted communication and secure storage with any external flash.
TESIC RISC-V is delivered as soft IP (RTL and netlist files) to CC compliant design centers, with additional services offered by Tiempo Secure to ensure future CC EAL5+ or other security certification, or as a GDS hard macro to the certified fab, with the guarantee to pass CC EAL5+ PP0084 / PP0117 certification. It is available on multiple silicon processes.
TESIC CC EAL5+ Secure Element
Targeted designs are SoCs that require a security enclave highly protected against side-channel attacks and perturbation/fault attacks, and that execute secure software such as iSIM/iUICC, EMVCo payment, FIDO2 Web authentication, V2X HSM protocol and/or other security routines for the SoC system, including secure boot, secure OTA firmware update, secure storage and secure debug.
TESIC includes a secure MCU, secure cryptographic hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. Memory sizes, cryptographic accelerators and interfaces can be customized according to customer requirements.
TESIC supports any non-volatile memory (NVM) architecture, including embedded flash and MRAM, and the use of any external flash chip. It implements a CC EAL5+ PP0084 / PP0117 compliant security protocol for the encrypted communication and secure storage with any external flash.
TESIC is delivered as a GDS hard macro to the certified fab, with the guarantee to pass CC EAL5+ PP0084 / PP0117 certification of the chip integrating this macro. It is available on multiple silicon processes, including GF 55 LPx, TSMC 40 ULP, GF 22 FDX and TSMC 16 FFC.
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