As the market leader in the EDA-to-ATE vector translation and validation solution space since 1979, TSSI’s vector translation tool has helped generations of IC devices getting tested on all market leading testers with quality test patterns.  TSSI’s virtual test methodology models tester instrumentation in a Verilog simulation environment for pre-silicon validation of test patterns and test program configuration with the device-under-test (DUT) for low power verification, high speed protocol debug, and ATE-specific mixed-signal validation.