Yonga Technology Microelectronics


YONGATEK, is founded in 2014 at Teknopark Istanbul by expert staff on ASIC/FPGA/SoC design and verification. YONGATEK’s core team has serious experience in industry leading companies such as ALCATEL, ST, ST-ERICSSON and ERICSSON. Main focus areas are:


  • FPGA, ASIC and SoC Digital Design Services with inhouse/customer licenses
  • SystemVerilog based UVM (Universal Verification Methodology) Verification Services with inhouse/customer licenses
  • RISC-V based ASIC/SoC Verification Services
  • DO-254 Compatible IP Design and Verification Services
  • Image and Video Algorithms and Implementation on Hardware (CPU, GPU, FPGA)
  • H264/HEVC Video Encoding/Decoding Algorithms and Develop FPGA/ASIC Ips
  • Develop Stellate and 5G Communications FPGA/ASIC Ips (BHC, LDPC, Turbo Decoder, DVB-S2 and DVB-RCS)
  • Video Tracker and Video Enhancement Applications
  • Embedded Firmware Development (Zynq, ARM, RISC-V cores)
  • Develop Computer Vision, AI and ADAS applications



YONGATEK team have completed many FPGA and ASIC projects for design and verification with DO-254 Compliance. Services provided by YONGATEK:

System Design

  • Specification
  • System Model Development
  • Requirement Management and Traceability

Gate Level Simulation

  • STA for hand-off before backend

FPGA prototyping for ASIC with big CTS boards

Physical Design

  • Floor Planning
  • Place and Route
  • DRC


  • High Level Design
  • Micro Architecture Documentation
  • RTL Coding with VHDL or Verilog
  • Functional Simulations
  • Directed Tests
  • System Verilog based UVM Tests
  • Coverage Analysis
  • Formal Verification

Verification and Test Supports

  • STA for sign-off before tape-out
  • Test Pattern Generations

Tape-out and Fabrication

Chip Validation

Cost effective Supply Chain Management

Logic Synthesis

  • Constraints
  • DFT (Design for Tests) Implementation

ASIC Implementation and Verification


  • SYNOPSYS Design Flow with inhouse licenses
  • Front-End flow: 6 Engineers (Synthesis, Timing Analysis, DFT)
  • Back-End flow: 1 Engineer



  • Mentor, Synopsys, Aldec flow
  • 15 UVM and RISC-V Experienced Engineers
  • 14 Completed UVM Verification Projects
  • DO-254 Complience
  • Requirements Management
  • 000+ Verified Requirements
  • Coverage Analysis

DO-254 Compliance

YONGATEK team have great experience in DO-254 Compliance.       Services provided by YONGATEK:

  • DO-254 Training and Consulting
  • DO-254 Documentations
  • Requirements and Traceability
  • FPGA/ASIC Flow for DO-254 Compliance
  • System Verilog Based UVM Verification
  • Coverage Analysis
  • FPGA Level In-Target Testing


Expertise at the following areas:

  • WLAN
  • HyperLAN
  • FEC (Turbo Decoder, LDPC)
  • Satellite Communication
  • Line-of-Sight Communication

PCB Design and Verification

YONGATEK team have implemented many PCB projects for design and verification in different areas:

  • High speed, High Density, Fine Pitch, multi-layer digital PCB designs
  • Bus routing, differential pairs, matched lengths.
  • PCB Designs for space, military, medical and commercial applications
  • PCB Designs with complex SoCs
  • High Speed Backplane Cards
  • Different power cards
  • Digital, Analog, RF, Power, Mixed Technologies
  • Radial Layouts and Non-standard Geometries
  • Planning and Requirements
  • Schematic Design
  • Schematic Verification
  • Detailed Design
  • Layout
  • Signal Integrity Analysis
  • PCB Production and Assembly
  •  PCB Tests

IP Cores

Video Controller

The H.264 hardware encoder is designed as a modular system with small, efficient, low power components doing well defined tasks. The principal design aim was to make a scalable encoder for megapixel images suitable for use in camera heads and low power recorders.


IP Specification:


  • Supports 4: 2: 0, 4: 2: 2 and 4: 4: 4 YCbCr digital video input.
  • Processing speed per pixel supports 2.5 clk cycles.
  • 16 video lines algorthmic encoding latency
  • No CPU required for encoding
  • Provides superior compression ratio up to Full HD and high quality video data.
  • Supports CBR (Constant bit rate), VBR (Variable bit rate).
  • Provides CAVLC coding.
  • Supports Avalon-ST / AXI4 interface.
  • Provides low external memory bandwidth usage.
  • Provides easy integration within the system.

Forward Error Correction

DVB-RCS Turbo Decoder IP:


  • DVB-RCS (ETSI EN 301 790) 8-state Duo-binary CTC (Convolutional Turbo Code)
  • Iteration: 1-10
  • Blok size: 8 – 510 bytes
  • ETSI EN 301 790 depuncturing
  • AWGN (Additive White Gaussian Noise) channel
  • BPSK, QPSK, 8-PSK, 16-APSK demodulation
  • Up to 110 Mbit/s throughput @125MHz
  • MATLAB floating and fixed point algorithm
  • Implemented on Xilinx Kintex-7 FPGA
  • Being used in Turksat-6A satellite
  • Gains up to 4 dB compared to convolutional codes


ytAES: ytAES core has been implemented according to the Advanced Encryption Standard and can be configured to perform either encrypt or decrypt for 128-bit blocks of input data by using key lengths of 128-196-256. The implementation is an ideal solution for low power and high-speed applications with a simple interface.


VISEC: VISEC is an extension IP family developed to work with any encryption core (AES, DES etc.) to increase the throughput by reducing the number of bits needed to be encrypted without having any security weakness. VISEC family needs to be used with high entropy data sets like Huffman-H263-H264-H265 etc. The input data then shuffled and split into dynamic two pieces named core and payload, according to our algorithm. After that, only the core part is encrypted and ready to be sent as an output. Currently there are 3 versions of VISEC family that have some architectural differences.

RISC-V Verification

YONGATEK RISC-V verification platform offers a comprehensive verification environment to solve the problem for a complete RISC-V functional verification suite that is needed by ASIC and FPGA system designers. Leveraged by YONGATEK’s deep UVM expertise, YONGATEK RISC-V verification platform includes system-level and block-level verification of any RISC-V based SoC and includes in-house developed cache and branch prediction simulators to verify the functionality of the most performance critical components inside a processor.



  • System/block-level SoC verification
  • YONGATEK cache simulator
  • YONGATEK branch prediction simulator
  • System/block level functional and stress tests
  • Peripheral verification with 3rd party VIP
  • Debugging via OpenOCD, GDB, and JTAG
  • Support for both Synopsys VCS and Mentor Graphics Questa simulators
  • FPGA prototyping
  • Design rule checking

Communication Controller


  • 10/100/1000/10G