Turkey
YONGATEK, is founded in 2014 at Teknopark Istanbul by expert staff on ASIC/FPGA/SoC design and verification. YONGATEK’s core team has serious experience in industry leading companies such as ALCATEL, ST, ST-ERICSSON and ERICSSON. Main focus areas are:
YONGATEK team have completed many FPGA and ASIC projects for design and verification with DO-254 Compliance. Services provided by YONGATEK:
System Design
Gate Level Simulation
FPGA prototyping for ASIC with big CTS boards
Physical Design
Design
Verification and Test Supports
Tape-out and Fabrication
Chip Validation
Cost effective Supply Chain Management
Logic Synthesis
DESIGN:
VERIFICATION:
YONGATEK team have great experience in DO-254 Compliance. Services provided by YONGATEK:
Expertise at the following areas:
YONGATEK team have implemented many PCB projects for design and verification in different areas:
The H.264 hardware encoder is designed as a modular system with small, efficient, low power components doing well defined tasks. The principal design aim was to make a scalable encoder for megapixel images suitable for use in camera heads and low power recorders.
IP Specification:
DVB-RCS Turbo Decoder IP:
ytAES: ytAES core has been implemented according to the Advanced Encryption Standard and can be configured to perform either encrypt or decrypt for 128-bit blocks of input data by using key lengths of 128-196-256. The implementation is an ideal solution for low power and high-speed applications with a simple interface.
VISEC: VISEC is an extension IP family developed to work with any encryption core (AES, DES etc.) to increase the throughput by reducing the number of bits needed to be encrypted without having any security weakness. VISEC family needs to be used with high entropy data sets like Huffman-H263-H264-H265 etc. The input data then shuffled and split into dynamic two pieces named core and payload, according to our algorithm. After that, only the core part is encrypted and ready to be sent as an output. Currently there are 3 versions of VISEC family that have some architectural differences.
YONGATEK RISC-V verification platform offers a comprehensive verification environment to solve the problem for a complete RISC-V functional verification suite that is needed by ASIC and FPGA system designers. Leveraged by YONGATEK’s deep UVM expertise, YONGATEK RISC-V verification platform includes system-level and block-level verification of any RISC-V based SoC and includes in-house developed cache and branch prediction simulators to verify the functionality of the most performance critical components inside a processor.
Features:
Ethernet:
SPI
I2C
I2S
UART
