412 Views

What is an ASIC and how it is being made?

October 03, 2018, anysilicon

ASIC stands for Application Specific Integrated Circuit,or in other words a chip that is being designed for a specific task.

 

 

Those Integrated Circuits (IC) are usually a combination of Analog circuit such as clock, amplifier and denoising circuit and Digital Block such as multiplexersregistersarithmetic logic units (ALUs), and computer memory. Basically Digital plane is being used for discrete signals [1,0] and Analog is being used for continuous signals (1–0).

 

 

Figure 1: Digital signals vs. analog signals

 

Denoising in the analog plane

 

 

So lets say our input signal supposed to look like a rectangle (Digital signal) and we added some noise on top of that signal we can now notice that the Signal with noise is no longer 1/-1 it is actually get up to 2 and down to -2. So with simple filtering (Analog design circuit) we can now see we managed to get the noise signal to something similar to the original.

 

Figure 2: Signal with noise

 

 

Digital circuit example — Half Adder


We will need Digital design circuits for an example to add 2 digital signals together.

 

 

Lets assume we have 2 black boxes. 1 black box can multiply the 2 input and the other one can do the say “I’ll let you pass only if one of you will be 1 and the other 0”. The first Black Box is called AND gate and the other one is called XOR. Hopefully you can now understand the table below, we just have 1 more question to answer. 1+1=2 right? I don’t think so :) 1+1=10 we are in the binary world after all, 10 = 0010 and turning a binary number to decimal is 0*2³+0*2²+1*2¹+0*2⁰=2. Seems okay now right? So we actually managed to get the following now: A+B = CS *** explain in words ***

 

 

Figure 3: Half adder

 

Okay, we managed to get an intuition of what is a Digital plane and what we can do with that and hopefully intuition for what is an Analog plane. Those 2 planes are being designed by different people and takes a lot of time to design, for big ASIC they can take months.

 

 

During the development of ASIC we keep on mixing those 2 planes in order get the fastest and the most power efficient chip oriented for mining.

 

 

So let’s talk how we design Digital circuits and how we design Analog circuit.

 

 

Digital circuits


In digital circuit design we have 2 main steps, Front-End step where we take a code and synthesize a schematic (netlist) out of it and second is the Back-End step where we take the netlist and design the layout, in other word a schematic where each gate will be placed and how we connect them.

 

 

Please read the following twice because I explain in details each of initials afterwards.

 

 

The Front-end Designer or Register-Transfer Level (RTL) designer, develop the design while using Field Programmable Gate Arrays (FPGA) or Simulation programs and programmed using Hardware Description Language (HDL) usually Verilog/VHDL.

 

 

FPGA? A Field Programmable Gate Arrays an integrated circuit designed to be configured by a customer or a designer after manufacturing. In other words you can upload your code into it and start debugging.

 

 

HDL? hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.

 

 

HDL languages are unique because they are being synthesized into logic gates and connectivity between those logic gates and also for each component we design we have to give the Ports. So actually it might be similar to other computer language but you construct and write in a different mindset. The output of the step is called a netlist, which is the text file of the synthesized logic gates and connectivity.

 

 

An example to a VHDL code of the digital block we designed and saw before:

 

 hald adder

Figure 4: VHDL code example of an Half Adder

In this example we see 2 sections, first one is the entity and the second one is the architecture. In the entity part you write the input and output signal names and what kind of data type is it. In the architecture we write down the connection between the input and output.

 

 

Figure 5: netlist example

 

 

An example to a netlist (the output of this step).

 

 

The first column is usually the type of the device and name then the connectivity and the last column is actually the multiply of this device.

 

 

The second step is called Back-end or physical design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

 

 

Figure 6: Layout of SHA-256 Accelerator Core

 

 

Analog circuits

 


The first step in the analog design is the analog circuit design/schematic design, the designer places devices like resistors, capacitors, inductors and transistors and later on simulate the design with different inputs and samples the output. Most of the design here is made by hand using design tools such as Virtuoso. We cannot translate into RTL code the design here because we are not facing a binary issue here. We are facing issues such as amplification and noise filtering.

 

 

The output of this step is a netlist similar to the output of the Front-end.

 

Figure 7: Common source amplifier schematic

The second step is a physical design it is very similar to the Back-end steps in the digital plane. But in this step some of the routing and placement are done manually at the moment because of analog signals. In general analog signals might be more sensitive to parasitic capacitance and resistance.

 

 

Parasitics are additional resistance and capacitance which we didn’t see while we designed the analog circuit. Those parasitics will always appear but some times they appear from wrong floor-planning such as placing 2 devices far away from each others or such as placing a sensitive circuit next a to really big capacitor which might cause unwanted capacitance on the circuit next to it. Those parasitic avoidance will cause us a floor plan constraint which most of them we will see only in the analog plain instead of the digital. The output of this step is called Masks, similar to the output of the Back-end.

 

 

Figure 8: Inverter layout design

 

 

Manufacturing 

 


Last step in the ASIC creation is the manufacturing. I’ll divide it into 3 processes Mask making, Wafer making and Cutting. I’ll have to give you an intuition for couple of things before we continue.

 

 

Wafer — also called a slice or a substrate, is a thin slice of a crystalline silicon. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as dopingor ion implantationetchingdeposition of various materials, and photolithographic patterning.

 

 

wafer

Figure 9: Silicon Wafer

 

 

 

Mask — Unlike the masks we know in those masks we uncover the places we want to print in them very similar to stencil. But instead of painting we use the microfabrication process steps we mentioned before.

 

 

maskset

Figure 10: Metal mask for semiconductor manufacturing

 

 

 

 

 

 

Mask making — We take the layout design (plan for the masks) from the Digital and Analog plane merge them and then creating mask for each layer. What are layers? There are many layers in each ASIC design but i’ll give you an example for two of them. The first one is called Via mask/Interconnect and other is a Metal mask. Via mask is creating holes in specific places in order to inject metal so i could connect between 2 metals and Metal mask is where you print the metal.

 

 

Figure 11: ASIC masks for the lithography process

 

 

 

 

Wafer making — We take the masks and using different microfabrication process steps on each mask we started creating the ASIC (Each layer at a time). On each wafer we create couple of ASICs simultaneously

 

 

Chip on silicon wafer isolated on white

Figure 12: Wafer with hundreds of ASICs

 

 

 

 

 

 

 

 

Cutting — Last step is cutting/dicing the ASICs on the wafer.

 

 

computer cpu or central processor unit chip on mainboard.Technology background with computer processors CPU concept and blue circuit, board texture.

Figure 13: ASIC in final package

 

 

We are now ready for packaging and send out the ASIC.

 

 

_________________________________

This is a guest post by Adi Szeskin.

Recent Stories