Category Archives: IP Cores

AnySilicon Guidelines for Semiconductor IP Core Selection

November 17, 2016, anysilicon

ip-core

The semiconductor IP core market has grown dramatically in the last 10 years. There are literally hundreds of IP core suppliers in the market providing almost every possible functionally –  from DC/DC and PLLs to Bluetooth and CPU cores. This large number of vendors and IP cores makes the selection

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Siemens to buy EDA vendor Mentor Graphics

November 14, 2016, anysilicon

mentor

Siemens is further building its Vision 2020 to shape Digital Industrial Enterprise by expanding its unique portfolio for industrial software. Siemens and Mentor Graphics (NASDAQ: MENT) (“Mentor”) today announced that they have entered into a merger agreement under which Siemens will acquire Mentor for $37.25 per share in cash, which

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SilabTech Announces Release of Trace Port PHY (HSSTP) for debug of Multiple Cores designs

November 04, 2016, anysilicon

hsstp-silicon-results-at-625gbps

Bengaluru (India) – Oct 25th, 2016 –SilabTech, a leading supplier of high speed serial interface intellectual property designs (IP cores) announced today the release of its High Speed Serial Trace Port (HSSTP) PHY. This IP Core is silicon proven on TSMC 28HPC and was successfully delivered to a Tier-1 global

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Espressif Licenses CEVA IP Core in IoT Chip

November 03, 2016, anysilicon

ceva-soc-platform-ip-chip_whitebg

EVA, Inc. (NASDAQ: CEVA), the leading licensor of signal processing IP cores for smarter, connected devices, today announced Espressif Systems, a leading fabless semiconductor company providing low power wireless solutions for the Internet of Things (IoT) applications has licensed and deployed the RivieraWaves Bluetooth dual mode technology in its new ESP32 chip.
 
Espressif

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What is RISC-V? Why do we care and why you should too!

October 28, 2016, anysilicon

risc-v

I’d like to start by talking about the biggest misconception regarding RISC-V. Many of you who have heard about RISC-V likely believe it is an open-source processor … but it is not.
 
So what is it?
RISC-V is an open specification of an Instruction Set Architecture (ISA). That is,

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Hisense selects their SoC Fabric IP for IoT from Dolphin Integration

October 24, 2016, anysilicon

hisense

Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing with

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