SEOUL, South Korea – January 9, 2025 — QUALITAS SEMICONDUCTOR CO., LTD. (hereinafter referred to as “Qualitas”) (KOSDAQ: 432720), a leading provider of high-speed interconnect solutions, has announced the supply of its 4nm PCIe 6.0 PHY IP to VeriSilicon Inc., a global design house.
This agreement was part of
SerDes IPs serves as the backbone of high-speed data transfer, converting parallel data into serial form for transmission, and vice versa at the receiving end. With various configurations, including single-channel and multi-channel setups, and advanced signaling techniques such as PAM4, the selection of the right SerDes Intellectual Property (IP) becomes
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Shanghai, China – November 29, 2024–VeriSilicon (688521.SH) today announced a strategic partnership with LVGL, the leading open-source graphics library for embedded systems, to support VeriSilicon’s low-power 3D and VGLite 2.5D GPU technology within the LVGL library. This partnership aims to optimize performance and expand graphic processing capabilities for a wide
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Cadence has announced a groundbreaking achievement with the development and successful tapeout of its first Arm-based system chiplet. This innovation marks a pivotal advancement in chiplet technology, showcasing Cadence’s commitment to driving industry-leading solutions through its chiplet architecture and framework.
The First System Chiplet
In a significant leap forward,
Embedded non-volatile memories (eNVM) are memory blocks that are directly integrated semiconductor fabrication on the same die. Since eNVM memories are non-volatile, the data is retained even when the power is off. In addition, eNVMs are reprogrammable and erasable multiple times. Compared to external non-volatile memory technologies, eNVMs have lower
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Woodcliff Lake, New Jersey — November 19, 2024—Semiconductor intellectual property provider CAST, in collaboration with Silesia Devices, today announced a new IP core that implements the Serial Peripheral Interface for Automotive Safety (SafeSPI), an emerging open standard that adds Functional Safety and interoperability features to the de-facto Serial Peripheral Interface
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