May 24, 2015, anysilicon
Clock gating is a low power design technique involving shutting down (gating) the clock when the module to which the clock feeds doesn’t need to operate. Clock gating is the most commonly used technique to save dynamic power because clock switching corresponds to over 50% of the total dynamic power dissipated in the entire chip. While there are many techniques to employ clock gating, the most robust of them use a clock gating integrated cell controlled by an enable signal dictating whether or not to gate the clock feeding the flops in its downstream. Other techniques to gate the clock using an AND gate or an OR gate are prone to glitches and must be used with special care.