ASIC RTL Design and Automation Engineer, University Graduate

Join Google as an ASIC Design Engineer, where you'll play a pivotal role in shaping the future of AI/ML hardware acceleration. This position involves developing cutting-edge TPU technology that powers Google's most demanding applications, contributing to innovative silicon solutions that impact millions worldwide.

Responsibilities:

• Develop SystemVerilog RTL to implement logic for ASIC products.
• Create and review design microarchitecture specifications.
• Develop methodology and tooling for design automation.
• Collaborate with Design Validation (DV) teams to create test plans for verifying and debugging design RTL.
• Work with Physical Design teams to ensure designs meet physical requirements and achieve timing closure.

Qualifications:

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience in silicon engineering through internships, academic research, or publications.
• Proficiency in a scripting language such as Python or Perl.
• Experience in Verilog or SystemVerilog.

Skills:

• Creating digital designs, including synchronous and asynchronous logic, state machines, and bus protocols.
• Developing scripts or tooling for design automation.
• Optimizing designs for performance, power, or area.