ASIC Feasibility Explained: Is a Custom ASIC Realistic for Your Product?

Many teams talk about doing an ASIC long before they know whether an ASIC is actually feasible.  In practice, ASIC feasibility is not a yes/no question.

It is a balance of economics, risk, schedule, and technical reality.

This article explains what really makes an ASIC project feasible — and why many promising ideas should not start with custom silicon.

What “ASIC feasibility” actually means

An ASIC is feasible when:

• the technical problem is clear
• the economic case holds over the product lifetime
• the risks are understood and acceptable

It does not mean:

• “we can design it”
• “it will be faster than FPGA”
• “unit cost will be lower at volume”

Those assumptions are where many projects fail.

The five pillars of ASIC feasibility

Volume and lifetime economics

ASICs rarely make sense for:

• very low volumes
• short product lifetimes
• unclear market demand

The feasibility question is not:

What is the unit cost at volume?

It is:

Can we amortize NRE, respins, and time over the product lifetime?

If volume is uncertain, feasibility is uncertain.

Power, performance, and BOM pressure

ASICs become feasible when:

• FPGA power consumption is unacceptable
• BOM cost must be reduced significantly
• form factor or performance cannot be met otherwise

If your product already meets targets on:

• FPGA
• SoC
• off-the-shelf silicon

Then ASIC feasibility is questionable, even if technically possible.

Design stability and iteration risk

Custom silicon rewards stable requirements.

ASIC feasibility drops sharply when:

• specifications are still changing
• interfaces are not locked
• “we’ll fix it in the next spin” becomes a strategy

Each respin:

• costs money
• adds months
• compounds schedule risk

An ASIC project is only feasible if iteration risk is intentional and planned.

Backend reality: packaging, test, and yield

Many ASIC feasibility discussions stop at RTL.

In reality, feasibility is often decided by:

• package availability
• pin count
• test strategy
• yield expectations

If backend assumptions are unclear, ASIC feasibility is unclear — regardless of how good the front-end design looks.

Time-to-market constraints

ASIC feasibility is tightly coupled to schedule.

If:

• missing a market window kills the product
• development timelines are rigid
• silicon delays cannot be absorbed

Then ASIC feasibility may depend on:

• MPW vs full mask
• phased deployment
• hybrid strategies

Time is often the most underestimated feasibility factor.

Why many ASIC ideas fail feasibility checks

Common failure patterns include:

• assuming volume that never materializes
• underestimating verification effort
• ignoring backend and test constraints
• choosing aggressive nodes too early
• committing to full mask before learning

None of these are technical incompetence — they are decision mistakes.

ASIC feasibility is not the same as “should we do ASIC now”

A project can be:

• feasible, but premature
• technically possible, but economically weak
• strategically right, but operationally risky

This is why feasibility should be evaluated before committing to:

• NRE
• foundry selection
• mask strategy

Check ASIC feasibility for your project

Instead of guessing, you can run a quick feasibility check based on:

• volume expectations
• power and cost pressure
• schedule risk
• design stability

👉  Run the ASIC or NOT decision tool

This helps you decide whether to:

• stay on FPGA / SoC
• prepare for MPW
• commit to custom silicon

What happens after ASIC feasibility is confirmed

Once ASIC feasibility is clear, the next decisions are:

• MPW vs full mask
• node selection
• backend planning
• production scaling

Feasibility is the gate — not the finish line.

Final takeaway

ASIC feasibility is not about ambition or technical skill.

It is about alignment between product reality and silicon economics.

When feasibility is clear, ASICs are powerful enablers.

When it is ignored, they become expensive lessons.

Before committing to custom silicon, make feasibility explicit.