Developing a custom ASIC is a significant investment, and validating the design before committing to volume production is essential. ASIC prototyping services allow semiconductor companies, startups, and product manufacturers to evaluate chip functionality, verify performance, and reduce technical risks before launching full-scale manufacturing.
ASIC prototyping can involve two different approaches: using FPGA-based development boards to validate digital functionality before fabrication, or manufacturing physical prototype chips through semiconductor foundries using multi-project wafer (MPW) shuttle runs or dedicated wafer runs.
Both methods play an important role in ASIC development, but they serve different purposes. FPGA prototyping provides an opportunity to validate digital hardware and software integration, while silicon prototyping enables engineers to measure the actual electrical characteristics and manufacturing behavior of the final integrated circuit.
For companies developing a new ASIC, choosing the right prototyping strategy can significantly influence development costs, project schedules, and the likelihood of a successful transition to production.
AnySilicon helps companies identify semiconductor foundries, ASIC design houses, packaging providers, and testing companies that can support ASIC prototyping projects.
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ASIC prototyping is the process of validating an application-specific integrated circuit before committing to full-scale production.
The objective is to identify design issues, verify system functionality, and evaluate whether the ASIC meets its electrical, functional, and performance specifications.
Depending on the development stage, prototyping can involve digital hardware emulation, FPGA-based hardware platforms, or actual silicon manufactured by a semiconductor foundry.
There are two main approaches.
FPGA-based prototyping uses programmable logic devices to implement and test portions of an ASIC design before manufacturing the actual silicon.
Engineers can map digital RTL designs onto one or more FPGAs to evaluate functionality, hardware/software interactions, system integration, and selected real-time operating scenarios.
FPGA prototyping is particularly useful for complex digital ASICs and system-on-chip (SoC) designs containing processors, interfaces, memory controllers, and digital signal-processing functions.
However, FPGA prototypes cannot fully reproduce the transistor-level characteristics, timing, power consumption, analog behavior, or manufacturing variations of the final ASIC.
Silicon prototyping involves manufacturing physical ASIC samples using the intended semiconductor fabrication technology.
The fabricated prototype can be packaged, tested, and characterized to determine whether the circuit meets its specifications.
Silicon prototypes are especially important for evaluating:
For companies developing custom analog ICs, mixed-signal ASICs, sensor interfaces, power management ICs, or RFICs, physical silicon prototyping is often essential before entering production.
Before manufacturing an ASIC, companies may use FPGA prototyping boards to evaluate digital functionality and software integration.
A common question is whether to purchase a commercially available FPGA prototyping platform or develop a custom board.
Commercial FPGA prototyping boards offer an established hardware platform that can reduce the need for custom PCB development.
Depending on the selected platform, these boards may include high-capacity FPGAs, external memories, high-speed interfaces, debugging connections, and expansion options.
They are attractive when the primary objective is to evaluate an ASIC’s digital logic or software integration without developing specialized hardware.
However, commercial boards may impose limitations related to available FPGA resources, I/O configuration, interface connectivity, or system architecture.
A custom FPGA prototyping board provides greater control over the hardware configuration.
This may be necessary when the ASIC requires specialized interfaces, unique memory arrangements, unusual form factors, or integration with application-specific hardware.
The trade-off is the additional engineering effort associated with PCB design, signal integrity, component procurement, fabrication, assembly, and debugging.
A custom board may be justified for complex projects or when existing FPGA platforms cannot satisfy the design requirements.
FPGA prototyping is generally most useful for validating digital logic and system behavior. It cannot replace physical silicon validation when actual transistor performance, analog characteristics, RF behavior, or fabrication-related effects must be measured.
Once the ASIC architecture is sufficiently mature and the design has completed the required verification and sign-off activities, the next major step is often a silicon prototype.
This is where multi-project wafer services and semiconductor foundry prototyping become particularly valuable.
A Multi-Project Wafer (MPW) run allows several independent chip designs to share a common semiconductor manufacturing run.
Instead of one customer paying for an entire dedicated photomask set and fabrication lot, multiple projects share relevant manufacturing and mask expenses.
Each participating company receives prototype dies corresponding to its own design.
This approach can significantly reduce the initial fabrication cost of obtaining prototype silicon compared with a dedicated wafer run.
MPW shuttle services are commonly used for:
MPW programs are offered by various semiconductor foundries and access partners, with different supported technologies, schedules, minimum areas, and commercial requirements.
For example, TSMC operates its CyberShuttle program, GlobalFoundries offers GlobalShuttle, and Tower Semiconductor operates an MPW Shuttle Program.
These programs differ in process availability, submission requirements, pricing, and prototype delivery arrangements.
The primary advantage of MPW manufacturing is the ability to obtain actual silicon without bearing the complete cost of a dedicated mask set.
Other benefits include access to established foundry processes, an opportunity to validate custom IP, and the ability to measure silicon performance before making a larger manufacturing commitment.
MPW runs can also support a company’s transition from a completed design to commercial production.
MPW services also have limitations.
Most shuttles operate according to predefined submission deadlines and fabrication schedules. Missing a tape-out date may require waiting for a subsequent run.
Customers may also face restrictions involving design area, process options, metal layers, prototype quantities, or special manufacturing requirements.
The number of prototype dies available may be limited, and additional engineering samples may require separate arrangements.
For these reasons, MPW availability should be considered early in the ASIC development schedule rather than only after the design is completed.
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Companies developing ASIC prototypes must decide whether to use a shared MPW shuttle or fund a dedicated wafer run.
The most appropriate choice depends on the project’s development objectives, technology requirements, expected quantities, budget, and manufacturing schedule.
| Factor | MPW Shuttle Run | Dedicated Wafer Run |
|---|---|---|
| Photomask costs | Shared across projects | Customer funds dedicated tooling |
| Initial fabrication investment | Generally lower | Generally higher |
| Schedule | Fixed shuttle deadlines | Dependent on dedicated fab scheduling |
| Design area | Subject to MPW allocation rules | Greater flexibility, subject to reticle limits |
| Prototype quantities | Usually limited | More suitable for larger sample quantities |
| Process options | Restricted to available shuttle offerings | Potentially more flexibility |
| Typical application | First silicon, IP validation, engineering samples | Larger engineering lots, qualification, production preparation |
MPW manufacturing is often appropriate when the company needs a limited number of silicon samples to validate the design.
It is particularly attractive for early-stage ASIC development, IP verification, analog circuit characterization, and projects where minimizing initial mask investment is important.
A dedicated run may be more appropriate when larger quantities of silicon are required, when the process configuration is incompatible with available MPW services, or when a project requires greater manufacturing flexibility.
Dedicated runs may also be required for certain qualification programs or production-oriented engineering activities.
Importantly, MPW prototyping is not necessarily limited to very advanced digital semiconductor processes. Mature CMOS, analog, mixed-signal, BCD, RF, and specialty technologies may also be available, depending on the foundry and specific shuttle offering.
Selecting a semiconductor foundry for ASIC prototype manufacturing is not simply a matter of choosing the smallest available technology node.
The foundry process must support the electrical characteristics, circuit functionality, manufacturing requirements, and commercial objectives of the ASIC.
Different ASIC applications require different semiconductor manufacturing technologies.
Digital ASICs and compute-intensive SoCs may prioritize logic density, performance, and power efficiency.
Analog and mixed-signal ASICs may require precision passive components, specialized transistor options, higher operating voltages, or particular analog device characteristics.
Power management ASICs may need BCD technologies, while high-frequency RF applications may require RF CMOS, SiGe, or other specialized processes.
The selected process should match the product requirements rather than the latest available technology node.
Before starting an ASIC design, the engineering team must have access to the appropriate Process Design Kit (PDK), design rules, simulation models, libraries, and relevant semiconductor IP.
The availability and maturity of these resources influence the effort required to design and verify the ASIC.
Foundry shuttle schedules should be reviewed early in development.
The design team needs sufficient time to complete verification, physical sign-off, and submission requirements before the MPW deadline.
A late design change can affect the tape-out schedule and delay the delivery of prototype silicon.
Foundry selection should also consider whether the process will remain suitable for the intended commercial product.
A successful prototype is only one stage in the product lifecycle.
Companies should evaluate production wafer availability, expected costs, packaging options, qualification requirements, and long-term manufacturing support.
Manufacturing an ASIC prototype requires coordination between the chip design team, semiconductor foundry, and potentially several additional service providers.
Although the exact process varies by technology and supplier, the development flow generally includes the following stages.
The project begins with the ASIC’s functional and electrical specifications.
These may include performance requirements, supply voltages, interfaces, power consumption, operating temperature, package requirements, and target production volume.
The design team develops the required analog, digital, or mixed-signal circuitry using the selected foundry’s design environment.
Before fabrication, the ASIC must undergo appropriate functional and physical verification.
For digital ASICs, this may involve RTL simulation, formal verification, static timing analysis, and other sign-off activities.
Analog and mixed-signal projects may require transistor-level simulation, process-voltage-temperature analysis, mismatch analysis, and post-layout simulation.
The verification strategy depends on the ASIC architecture and technology.
Once the circuit design is complete, the physical layout is prepared for manufacturing.
Before tape-out, the design must satisfy foundry requirements, which may include design rule checking (DRC), layout-versus-schematic verification (LVS), electrical rule checks, density requirements, and additional technology-specific sign-off checks.
The final design database is generally submitted using an accepted layout format such as GDSII or OASIS.
The foundry or MPW service provider reviews the submission before manufacturing.
After acceptance, the design proceeds to mask preparation and semiconductor wafer processing.
For an MPW shuttle, multiple customer designs are combined into the shared manufacturing arrangement.
The wafers undergo the required semiconductor fabrication steps, including lithography, deposition, etching, implantation, and metallization.
The exact process flow depends on the selected technology.
Once fabrication is complete, the ASIC dies may require inspection, wafer probing, dicing, and packaging.
Some customers choose to evaluate bare dies, while others require packaged engineering samples that can be mounted onto evaluation boards.
Packaging decisions should consider pad layout, electrical connections, thermal requirements, signal integrity, and the intended testing environment.
The first fabricated ASIC samples are evaluated against the design specifications.
Typical testing activities may include:
Functional testing and interface verification.
Power consumption measurements.
Timing and performance characterization.
Analog accuracy and noise measurements.
RF performance measurements.
Temperature and voltage testing.
Initial manufacturing yield evaluation.
The objective is to understand whether the ASIC operates as intended and whether its measured performance agrees with the design simulations.
First-silicon results determine the next stage of the project.
If the prototype meets the required specifications, the company may proceed with further characterization, qualification, production test development, or manufacturing scale-up.
If significant problems are identified, a design revision and additional tape-out may be required.
Therefore, an ASIC prototyping budget should account for the possibility of more than one silicon iteration.
An ASIC prototype is not necessarily ready for evaluation when the foundry delivers the fabricated wafers.
Depending on the project, additional semiconductor services may be required to prepare usable engineering samples.
Wafer-level testing can identify defective dies, verify basic functionality, and measure selected electrical parameters before packaging.
The testing strategy may use dedicated probe cards, automated test equipment, or specialized engineering setups.
Prototype packaging allows bare semiconductor dies to be assembled into packages suitable for electrical testing and system integration.
Possible options include QFN, BGA, ceramic packages, or other formats, depending on die size, pad arrangement, thermal requirements, frequency, and application.
Not every package is available economically for very small prototype quantities, so assembly options should be investigated early.
Evaluation boards provide the electrical environment needed to measure the prototype ASIC.
These boards may include power supplies, interface connectors, reference components, signal-conditioning circuitry, and communication interfaces.
For high-speed, RF, or precision analog applications, the evaluation board can significantly influence measured performance.
Silicon characterization determines how well the ASIC performs across the required operating conditions.
If the prototype does not meet specifications, failure analysis and additional electrical measurements may be needed to identify the cause.
These services can be essential for distinguishing between design defects, packaging issues, test setup problems, and manufacturing-related effects.
The cost of manufacturing an ASIC prototype depends on the semiconductor technology, die size, process options, prototype quantity, packaging requirements, and testing scope.
MPW fabrication can reduce the initial mask-related investment, but it does not eliminate the other costs involved in developing an integrated circuit.
A complete ASIC prototyping budget may include several categories.
If the design is not yet ready for tape-out, the project may require additional engineering services, such as RTL design, analog circuit implementation, physical design, verification, or sign-off.
These activities can represent a substantial portion of the overall development budget.
MPW prices are influenced by the selected foundry, technology node, allocated design area, process options, and commercial terms.
A larger ASIC may require more MPW area, while specialized manufacturing options can affect the available shuttle choices and price.
There is no single MPW price that accurately represents all foundries and technologies.
Prototype die packaging involves additional engineering and manufacturing expenditure.
Costs may include package design, bonding or interconnect development, assembly setup, tooling, and sample quantities.
Silicon testing can require specialized equipment, test boards, fixtures, and engineering support.
For analog, RF, high-speed, or highly integrated mixed-signal ASICs, characterization effort may be significant.
Not every ASIC succeeds on the first fabrication run.
If a silicon revision is required, the project may incur additional design, fabrication, and testing expenses.
Companies should evaluate their overall prototyping budget rather than considering only the initial wafer fabrication quotation.
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The best ASIC prototyping partner depends on the technical status of the project and the services the customer requires.
Some companies need only access to an MPW shuttle run. Others require a full turnkey solution that includes design completion, prototype fabrication, packaging, testing, and eventual production support.
Before selecting a supplier, consider the following questions.
Confirm that the supplier can access the foundry, process technology, and special device options needed by the ASIC.
This is particularly important for analog, RF, BCD, high-voltage, and other specialized technologies.
Some customers have a verified, manufacturing-ready layout database.
Others need assistance with physical sign-off, design-for-manufacturing checks, IP integration, or final layout preparation.
The scope of work should be clearly defined before requesting a quotation.
An MPW quotation may cover specific fabrication and sample-delivery activities without including package assembly, wafer probing, final testing, or characterization.
Ask the supplier to identify exactly which services are included and which require separate quotations.
The number of samples depends on the MPW service, project allocation, and commercial agreement.
Customers should confirm whether the deliverables are bare dies, packaged devices, tested samples, or another form.
If the prototype is part of a future commercial product, confirm the route to dedicated manufacturing and ongoing semiconductor supply.
The customer should understand whether the selected process, IP licenses, packaging solutions, and test strategies can support the intended production volume.
Companies requesting ASIC prototype manufacturing services should prepare as much of the following information as possible:
ASIC type: Digital, analog, mixed-signal, RF, power management, sensor interface, or another application.
Project status: Early concept, completed schematic, verified RTL, completed layout, or tape-out-ready GDSII/OASIS.
Foundry and process: Preferred foundry, technology node, and required manufacturing options.
Die size: Estimated or finalized chip dimensions.
Prototype quantity: Number of engineering samples required.
Packaging requirements: Bare die, QFN, BGA, or another package.
Testing requirements: Wafer sort, functional testing, characterization, or qualification support.
Tape-out schedule: Preferred submission date and required sample delivery timeframe.
Future production: Estimated annual wafer or chip volume and product lifetime.
Not every customer will have finalized all these details.
For early-stage projects, a semiconductor design house or turnkey ASIC provider can assist with foundry selection, process evaluation, and prototype planning.
A more complete specification generally allows suppliers to provide more accurate quotations and realistic development schedules.
FPGA prototyping implements a digital hardware design on programmable devices to evaluate functionality and system behavior before semiconductor manufacturing.
Silicon ASIC prototyping manufactures physical integrated circuits using a foundry process, allowing designers to measure actual chip performance and validate the design before production.
An MPW, or multi-project wafer, run combines several semiconductor designs within a shared manufacturing arrangement.
Participating customers share certain mask and fabrication expenses, reducing the initial cost of obtaining prototype silicon compared with a dedicated run.
Yes. MPW services allow companies to obtain limited quantities of prototype silicon without funding an entire dedicated mask set and wafer lot.
The quantity and delivery format depend on the foundry and specific shuttle offering.
Yes. Various foundries and access partners offer MPW programs supporting analog, mixed-signal, RF, BCD, and specialty semiconductor technologies.
Availability depends on the specific process and shuttle schedule.
Not necessarily. Initial enquiries can often be evaluated using the intended process, estimated die size, prototype quantity, and preferred tape-out date.
However, final fabrication submission requires a completed design database that satisfies the foundry’s requirements.
The timeline depends on the foundry, selected process, shuttle schedule, fabrication cycle, packaging requirements, and testing activities.
The complete timeline should account for the period between the design being ready and the selected MPW submission deadline, not only the time spent processing the wafers.
Prototype silicon may be useful for engineering evaluation, characterization, and selected qualification activities.
However, a successful MPW run does not automatically establish that a device is qualified or ready for volume production.
Further testing, reliability assessment, production process validation, and manufacturing preparation may be necessary.
The engineering team investigates the failure using simulation results, electrical measurements, test data, and, where appropriate, physical failure analysis.
Depending on the cause, the next step may involve changes to the design, packaging, test setup, or manufacturing approach.
A silicon revision may require another prototype run.
Developing an ASIC prototype requires the right combination of engineering expertise, semiconductor process technology, manufacturing access, packaging, and testing support.
Whether your project involves FPGA-based functional prototyping, an analog or mixed-signal first-silicon prototype, an MPW shuttle run, or a complete turnkey ASIC development program, selecting suitable semiconductor partners is an important step toward successful commercialization.
AnySilicon helps companies identify semiconductor design houses, foundries, packaging providers, and testing companies that can support different stages of ASIC development.
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