Belgrade, Serbia – December 20th, 2016 – HDL Design House, a provider of high-performance digital and analog IP cores and system-on-chip (SoC) design and verification services, has joined the ARM® Approved Design Partner program, through which leading SoC design houses are recognized by ARM as accredited partners in specific technologies
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It can be asked why design a dual port memory bit? Is this not a case of re-inventing the wheel? Not necessarily. Most memories are designed with speed being the main design goal. You achieve speed by limiting that range of voltages and temperatures that the memory will operate over.
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This is an interview with Moortec CTO, Oliver King about the thermal issues associated with modern ASICs and ponders the question How Hot is Hot? Oliver has been leading the development of compelling in-chip monitoring solutions to address problems associated with ever-shrinking System-on-Chip (SoC) process geometries. An analogue and mixed signal
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In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also
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Williston, VT October 17, 2016: asicNorth announced today they have created a complete development ecosystem specifically targeted toward custom “Internet of Things” (IoT) devices. The asicNorth “IoT Design EcoSystem” is formed by linking key partners in system design, semiconductor design and process technology areas. Joining asicNorth are SoC Solutions, Faraday
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Today, ASIC design flow is a mature process with many individual steps. ASIC design flow process is the backbone of every ASIC design project. To ensure design success, one must have: a silicon-proven ASIC design flow, a good understanding of the ASIC specifications and requirements, and an absolute domination over
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