Category Archives: Verification

Choosing the right VIP

In past few months, while interacting with customers, I came across a couple of cases where the VIP played a spoilsport. In one case, the IP & VIP were procured from the same vendor during the early phase of standard protocol evolution. One of the key USPs of the product was

Debugging in System Verilog Constrained Random Verification

70 % of ASIC design goes in verification and 70 % of verification goes in debugging.
 
Planning for the debugging goes a long way. Feature by feature the way we architect the test bench pay some attention as to how will it be debugged. This strategy will pay back

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place

Don’t Get Critical IP Cores from a ‘Supermarket’

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a tight schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your silicon