Category Archives: Verification

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place

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Don’t Get Critical IP Cores from a ‘Supermarket’

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a tight schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your silicon

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