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Understanding CoWoS Packaging Technology

In order to cater to the computing demands for high performance computing (HPC) and artificial intelligence (AI), a need for a scalable package was felt. Chip-on-wafer-on-substrate (CoWoS) refers to the advanced packaging technology that offers the advantage of a larger package size and more I/O connections. It allows 2.5D and 3D stacking of components to enable homogenous and heterogenous integration. Previous systems faced memory limitations and contemporary data centers employ the use of high bandwidth memory (HBM) to enhance memory capacity and the bandwidth. CoWoS technology allows heterogenous integration of logic SoC and HBM on the same IC platform.

 

Photo inspiration: TSMC

 

CoWoS Package Overview

 

CoWoS architecture encompasses both 2.5D horizontal stacking and 3D vertical stacking configurations, revolutionizing the traditional paradigm of chip packaging. This innovative approach allows for the stacking of various processor and memory modules layer by layer, creating chiplets that are interconnected to form a cohesive system. By leveraging through-silicon vias (TSVs) and micro-bumps, CoWoS facilitates shorter interconnect lengths, reduced power consumption, and enhanced signal integrity compared to conventional 2D packaging methodologies.

 

In practical terms, CoWoS technology enables the seamless integration of advanced processing units, such as GPUs and AI accelerators, with high-bandwidth memory (HBM) modules. This integration is particularly crucial for AI applications, where massive computational power and rapid data access are paramount. By colocating processing and memory elements within close proximity, CoWoS minimizes latency and maximizes throughput, thereby unlocking unprecedented performance gains for memory-intensive tasks.

 

Advantages of CoWoS Packaging

 

CoWoS technology offers multiple advantages:

 

Scaling and higher levels of integration: Traditionally, scaling of transistors in accordance with Moore’s Law has helped fulfil the need for increased performance. However, this has proved to be insufficient for modern applications like high performance computing (HPC), artificial intelligence, and even graphics processing units (GPUs). CoWoS allows stacking of chips on the same substrate, therefore reducing the interconnect delays between homogenous or heterogenous logic SoCs and between the HBMs.

 

Enhanced thermal management: The use of silicon interposers and organic interposers have greatly enhanced the thermal management capabilities of stacked integrated circuits. This directly improves the overall system reliability, longevity while minimizing the risks of thermal throttling.

 

Improved Power Integrity: The use of RDLs for power/ground networks within the interposer coupled with the use of deep trenched capacitors (DTC) allow for no compromise on the power integrity for high-speed applications and memory intensive applications.

 

Reduction in size and cost: CoWoS technology helps mounting multiple logic SoCs and HBMs on the same interposer and substrate. This is in stark contrast to traditional packaging technologies where multiple logic SoCs used to be mounted on a printed circuit board (PCB) and make the necessary connections in the package. This resulted in bigger packages and exacerbated the material costs and manufacturing overhead. CoWoS package is overall smaller and more cost efficient.

 

CoWos Technology Market Dynamics

 

Demand Drivers

 

  • The flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing has led to an increasing demand for computing power.
  • Modern society’s high demand for computing power has fueled the growth of AI chips, driving the need for advanced packaging solutions like CoWoS.
  • TrendForce’s data highlights the significant growth of AI server shipments, which reached nearly 1.2 million units in 2023, with an expected CAGR of 22% from 2022 to 2026.
  • The demand for AI chips, particularly GPUs with higher specifications of HBM, has resulted in tight capacity for TSMC’s CoWoS packaging, with NVIDIA being a major customer.

 

Supply-Demand Dynamics

 

  • TSMC’s CoWoS packaging capacity has been a bottleneck for AI chip output due to supply shortages, particularly in the interposer segment.
  • TSMC’s plans to double CoWoS capacity and invest in advanced packaging fabs aim to alleviate supply-demand imbalances by the end of 2024.
  • Other Taiwanese companies, including UMC, ASE Technology Holding, and Powertek Technology, are entering the CoWoS advanced packaging market, expanding capacity and offering alternative solutions.

 

Variants of CoWoS Technology

There are 3 class of CoWoS technologies currently in use:

 

CoWoS-S: This technology uses a monolithic silicon interposer along with through silicon vias (TSVs) to facilitate direct transmission of high-speed electrical signals between the die and the substrate. The monolithic silicon interposer, however, suffers from yield issues.

Figure 1: CoWoS-S Package

 

CoWoS-R: This technology replaces the silicon interposer of CoWoS-S with an organic interposer. The organic interposer has fine-pitched RDL to provide a high-speed connection between the HBM and the die or even between the die and the substrate. CoWoS-R offers superior reliability and yield in contrast to CoWoS-S because the organic interposer, being inherently flexible, acts as a stress buffer and mitigates the reliability issues arising due to a mismatch between the coefficients of thermal expansion between the substrate and the interposer.

Figure 2: CoWoS-R Package

 

CoWoS-L: This uses local silicon interconnect (LSI) along with RDL interposer together forming a reconstituted interposer (RI). In addition to the RDL interposer, it also the preserves the attractive feature of CoWoS-S in the form of through silicon vias (TSVs). This also mitigates the yield issues arising due to the use of large silicon interposer in CoWoS-S. In some implementations, it may also use through insulator vias (TIVs) instead of TSVs to minimize the insertion loss.

Figure 3: CoWoS-L Package

 

Understanding CoWoS Package Components

 

This section discusses the constituents of CoWoS-L package and the fabrication steps:

 

  1. CoWoS-L is a chip-last assembly because the interposer is fabricated first and then followed by stacking of the wafer die on top. Interposer stands out as one of the key raw materials in the CoWoS technology because multiple wafer-dies like SoC, HBM etc. are mounted on the interposer, and it enables efficient connectivity and communication between the chips. Once the interposer is fabricated, next step is creation of the through insulated vias (TIVs) in the wafer die.
  2. The known good dies (KGDs) are then mounted over the wafer. The gaps between the die and the TIV are filled with molding compound, after with CMP process is employed to obtain a planar surface.
  3. In the next step, two RDL layers are fabricated-
    1. One on the interposer front-side to connect the wafer and the substrate via μ-bumps.
    2. The second RDL on the interposer back-side to connect the interposer and the substrate via C4 bumps.

 

In addition to this, CoWoS-L technology also uses deep trench capacitors (DTC), which provide high capacitance density that enhances the electrical performance of the system. These capacitors act as charge reservoirs and fulfil the instantaneous current demand while running high-speed computing applications.

 

Challenges and Limitations

 

Manufacturing Complexity and Cost Considerations: CoWoS being a 2.5D/3D integration technique involves significant manufacturing complexity in contrast to its predecessors. The manufacturing complexity directly translates into increased cost of the chips using this package technology. This is cited to be one big reason for the increased cost of HPC and AI chips in recent times. The cost of testing a CoWoS also adds to the total cost.

 

Integration and Yield Challenges: 5D and 3D integrated circuits need to be tested just like any other integrated circuit to ensure that they are free of any manufacturing defects. Testing a 2.5D or a 3D integrated circuit is however far more challenging because each wafer die needs to be tested individually before mounting them on the interposer, and subsequently need to be tested again after mounting. In addition to this, the through silicon vias (TSVs) also need to be tested. Lastly, the large silicon interposers are particularly susceptible to manufacturing defects and may lead to yield loss.

 

Thermal Challenges: CoWoS packages suffer from thermal issues due to a difference in the coefficient of thermal expansion (CTE) between the interposer and the substrate. Using organic interposers do limit the thermal issues to some extent. The life of a solder joint can be greatly enhanced by using an underfill material which buffers the thermal mismatch between the silicon die and the substrate.

Similarly, on the front-side, the integrity of the redistribution layer (RDL) particularly underneath the two silicon dies is vulnerable to stress. The use of μ-bump underfill again acts as a stress buffer between the silicon dies and the RDL.

 

Electrical Challenges: CoWoS packages suffer from electrical challenges in the form of signal and power integrity issues.

(1) Signal Integrity:

  • Logic wafer-die to substrate interconnects: As the data rate rises, the interconnection experiences degraded signal transmission caused by the parasitic capacitance and inductance of the TSV. To address this issue, efforts are made to optimize the TSV to minimize capacitance and inductance.
  • Logic wafer-die to HBM: The bottleneck in eye performance for the interconnection between SoC and HBM is attributed to the parasitic resistance and capacitance of the interconnect.

(2) Power Integrity: CoWoS packages are typically used for high performance applications that have higher data toggle rates and low operating voltages. This makes these packages susceptible to power integrity challenges.

 

Applications of CoWoS Technology

CoWoS technology can support much higher number of transistors in a package in contrast to older packaging technologies like System-in-Chip (SiP). All applications that require significant amount of parallel computing, processing large vectors of data and ones that need high memory bandwidth are most suitable to use this technology.

Figure 4: Increase in transistor count with CoWoS Development

 

Some of CoWos applications are:

 

  1. High-Performance Computing (HPC).
  2. Artificial Intelligence (AI) and Machine Learning (ML).
  3. Networking and Data Centres.
  4. Graphics Processing Units (GPUs) and Gaming.

 

Case Studies and Success Stories

 

Many companies have thrived on the success of CoWoS packages. A few examples are:

 

  1. NVIDIA relies on CoWoS package for their AI chips.
  2. AMD is also exploring the use of CoWoS package for their AI chips.
  3. MediaTek has partnered with TSMC to use CoWoS for their networking ASICs.
  4. Broadcom resorts to the use of CoWoS-L for their ASICs catering to Deep Learning and Networking Applications.
  5. Global Unichip Corp. (GUC) has also partnered with TSMC to use CoWoS for their AI, HPC and networking applications chips. Read more.

 

Conclusion

CoWoS technology offers higher levels of integration allowing for integrated circuits to scale to meet the demands of growing compute capacity. The technology is consistently evolving to ensure better yields, robust power and thermal integrity and increasing the interposer area further to allow more wafers to share the same substrate. CoWoS will continue to fuel the growth of semiconductor industry over the next few years.

 

References

    1. “Test Challenges in Designing Complex 3D Chips: What in on the Horizon for EDA Industry”, by Sandeep K. Goyal.
    2. “Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2”, by Huang et al.
    3. “CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package”, by Hu et al.