Reply To: Why IC design is so expensive?
Production setup, Production Ramp-up, Production optimization (Yield optimization)
Device qualification (HTOL, ESD, LU, HTSL, ...)
Comparing FPGA with ASIC the ROI is solely relying on
1. reducing the overhead and thereby reduced the die size -> reduced die cost.
2. Business model - reduce the margins in the supply chain e.g. standard device 60% GM to ASIC 40%, to COT mode ...
3. Volume
Henrik
