What is the very first test to run in wafer sort

  • Author
  • #3303
    Mike Reeves

    Hello ALL, we are planning a wafer sort test for our digital chip in 40mn, there is an internal debate on what is the very first thing to test after touchdown, please share your thoughts…

    Regards, Mike.


    Hello Mike

    Without specific knowledge of the design it becomes a very general answer. Many Test Engineers have preferences for different sequences. Often, the critical design parameters e.g. low power, timing, etc. is the key to where your test shall start. In general, I suppose 40nm is chosen in a compromise between high complexity (Area) and power consumption and here I will recommend the following sequence:

    Standby current, leakage
    Steady stead current – one or more simple vector
    brings the circuit into known condition
    IDDQ (leakage test)
    Scan Test (Static test)
    Timing / Function pattern test at reel speed
    BIST, OTP, etc. …
    Communication (Ethernet, SPI, R232, etc. …)

    The list can easily change if you have a design where the Memory is the yield killer, then test connectivity and then memory before anything else.

    I do hope you can use my very general reply to your question.


Viewing 2 posts - 1 through 2 (of 2 total)

The forum ‘Forum’ is closed to new topics and replies.