ASIC Design Verification Engineer

Join Cisco's Silicon One team in San Jose, CA, where you will play a pivotal role in developing a unified silicon architecture for web-scale and service provider networks. This position requires onsite presence at least 4 days a week and offers a unique blend of resources from a large organization with the innovative culture of a smaller team.

Responsibilities:

• Set vision and strategy for ASIC verification methodology and execution across multiple programs and product lines.
• Serve as technical authority and mentor for verification teams, fostering technical excellence and innovation.
• Lead architecture and implementation of scalable, reusable verification infrastructure and methodologies.
• Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
• Influence ASIC architecture and design to enable robust verification and high-quality silicon.
• Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.
• Provide technical leadership in root cause analysis and resolution of complex issues during bring-up and post-silicon validation.

Qualifications:

• Bachelor's degree + 5 years of ASIC experience, or Master's degree + 3 years of ASIC experience, or PhD + 0 years of related experience.
• Experience in System Verilog and UVM methodology.
• Hands-on experience building reusable and scalable test benches from scratch.
• Experience with scripting using Perl and/or Python.

Skills:

• Experience with forwarding logic, parsers, or P4.
• Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.