ASIC Design Verification Engineering Technical Leader

Join Cisco's Common Hardware Group (CHG) to innovate hardware platforms that power the AI era, focusing on core Switching, Routing, and Wireless products. Collaborate with a global team of experts to drive full product development from design to production, shaping the future of technology.

Responsibilities:

• Participate in ASIC design verification for high-end switching products.
• Lead and maintain Design Verification (DV) environment infrastructure.
• Develop simulation models, test plans, and performance analysis.
• Construct testbench components like scoreboard, agents, and monitors.
• Collaborate with teams to debug issues during post-silicon integration.
• Ensure comprehensive verification coverage through code and functional coverage.
• Contribute to chip architecture definition and discussions.
• Mentor junior engineers on project tasks and problem-solving.

Qualifications:

• Bachelor’s degree in Electrical or Computer Engineering with 10+ years of ASIC Design and Verification experience, or a Master’s degree with 8+ years of experience.
• Experience with ASIC design and verification processes, debugging, and tools.
• Experience leading verification methodology (in UVM) for clusters/subsystems or full chip level.

Skills:

• Proficiency in System Verilog and UVM.
• Experience with emulation platforms (Veloce, Palladium, Zebu, HAPS).
• Familiarity with Linux, C/C++, and/or Python/Perl.
• Knowledge in Networking.