ASIC Engineer, Fullchip Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join its Infrastructure organization, focusing on developing innovative ASIC solutions for data center applications. This role involves working within an agile team to ensure the verification closure of design modules or sub-systems, utilizing various methodologies to achieve a bug-free design.

Responsibilities:

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Collaborate with cross-functional teams to ensure high design quality.
• Implement continuous Design Verification improvements using the latest methodologies and tools.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• Proven track record of 'first-pass success' in ASIC development cycles.
• Experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies.
• Familiarity with EDA tools and scripting languages (Python, TCL, Perl, Shell).
• Experience in architecting and implementing Design Verification infrastructure.

Skills:

• Expertise in SystemVerilog/UVM and C/C++ verification methodologies.
• Knowledge of SV Assertions, Formal, and Emulation techniques.
• Strong debugging and problem-solving skills.
• Ability to collaborate effectively with cross-functional teams.
• Experience in developing and executing verification plans and test scenarios.