ASIC RTL Design Engineer, ML Accelerators

Join Google's AI and Infrastructure team as an ASIC Design Engineer, where you'll contribute to the development of cutting-edge TPU technology that powers AI/ML applications. This role involves designing and implementing custom silicon solutions, focusing on high-speed digital designs and optimizing for performance, power, and area (PPA).

Responsibilities:

• Develop SystemVerilog RTL to implement logic for ASIC products.
• Create and review design microarchitecture specifications.
• Collaborate with design validation teams to create test plans for verifying and debugging design RTL.
• Work with physical design teams to ensure designs meet physical requirements and achieve timing closure.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with RTL design.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience in Verilog or SystemVerilog.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred).
• 5 years of experience in silicon engineering (preferred).
• Experience designing high-speed digital designs (preferred).
• Proficiency in scripting languages such as Python or Perl (preferred).