Published Date: February 21, 2026
Intel, Folsom, CA•Hybrid work
Job Description:
Join Intel's Full Chip Timing (FCT) Design Automation team as a CPU Core Pre-Silicon Validation/Verification Engineer. This role is pivotal in ensuring seamless timing closure and optimization across the backend flow, contributing to the development of world-changing technology that enriches lives globally.
Responsibilities:
- Perform functional verification of CPU logic to meet specification requirements.
- Develop IP verification plans, test benches, and verification environments to ensure coverage of CPU microarchitecture specifications.
- Execute verification plans and run system simulation models to verify design, analyze power and timing, and uncover bugs.
- Replicate, root cause, and debug issues in the pre-silicon environment.
- Implement corrective measures to resolve failing tests.
- Collaborate with CPU architects, RTL developers, and physical design teams to enhance verification of complex features and meet functional, performance, and power goals.
- Document test plans and drive technical reviews with design and architecture teams.
- Maintain and improve existing functional verification infrastructure and methodology.
- Participate in defining architecture and microarchitecture features of the CPU being designed.
Qualifications:
- Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or related field with 1+ years of relevant experience, or a Master's Degree in the same fields.
- 6+ months of experience in pre-silicon verification, software/programming languages, or System Verilog/Verilog/VHDL.
Skills:
- Proficiency in software/programming languages (C, C++, C#, Visual Basic/.NET, Perl, Python, Java).
- Experience with System Verilog/Verilog/VHDL, Verification, Validation, and/or VCS or similar Simulator.
- Knowledge of computer architecture and microarchitecture.
- Experience with coverage-driven validation and IP/SOC ASIC Validation.
- Familiarity with Specman E, System Verilog/OVM/UVM, and x86 core architecture.