DFT Design Engineer

Cadence is seeking innovative leaders to join our team, focusing on SoC/ASIC Digital Design with an emphasis on Design for Test (DFT). This role requires US citizenship and offers an opportunity to make a significant impact in the technology sector.

Responsibilities:

• Perform DFT insertion flows and basic scan chain insertion using synthesis or other software tools.
• Implement compression scan insertion, LBIST, and other scan technologies.
• Utilize memory build-in self-test (MBIST) techniques effectively.
• Generate Automatic Test Patterns (ATPG) to meet design test coverage goals.
• Debug and analyze failures to enhance fault coverage.
• Verify ATPG testbenches and troubleshoot simulation discrepancies.
• Apply knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687 standards.
• Conduct timing analysis and equivalency checks as needed.

Qualifications:

• 2-10 years of professional experience in SoC/ASIC Digital Design with a focus on DFT.
• Intimate knowledge of DFT insertion flows and related technologies.
• Experience with Cadence tools and flows is highly desirable.

Skills:

• Strong problem-solving skills with a disciplined and methodical approach.
• Ability to work collaboratively in a team environment.
• Self-driven and committed to working in a fast-paced project environment.
• Effective communication skills to engage with cross-functional teams including Architecture, Design, and customers.