FE Design Engineer

Sandisk is a leader in data solutions, known for its innovative Flash and memory technologies that power the digital world. With a commitment to sustainability and advanced manufacturing, Sandisk is recognized globally for its performance and quality. The company is seeking a seasoned Front-End (FE) Tools Engineer to bridge the gap between RTL design and back-end physical implementation, ensuring the integration of synthesis constraints and third-party IPs.

Responsibilities:

• Serve as the technical bridge between RTL design and back-end physical implementation.
• Define, maintain, and validate project-level synthesis constraints (SDC).
• Integrate synthesis constraints from third-party IPs into project synthesis constraints.
• Align third-party IP timing assumptions with top-level design intent.
• Resolve constraint conflicts between internal logic and external IPs.
• Provide expertise in SDC and STA for IP-level timing constraints.
• Assist designers with complex timing violations, particularly in cross-clock domains.
• Support LINT, CDC, and RDC processes.
• Provide ECO support.

Qualifications:

• Minimum 10 years of hands-on experience with FE implementation tools.
• Strong understanding of ASIC/SoC synthesis and timing methodologies.
• Experience with SDC, UPF/CPF, and formal equivalence checking (LEC).
• Familiarity with third-party IP integration (e.g., PCIe, DDR, SerDes).
• Proficiency in industry-standard EDA tools for synthesis, STA, and formal verification.

Skills:

• Strong scripting skills in Tcl and Python.
• Solid communication skills for cross-team and vendor collaboration.