Lead Digital Verification Engineer

Efficient is at the forefront of developing the world's most energy-efficient general-purpose computer processor, utilizing patented technology that consumes 100x less energy than current ultra-low-power processors. This innovation enables continuous AI/ML operations on minimal power sources, paving the way for a new era in IoT and computing. We are seeking a Design Verification Lead to spearhead the functional verification of complex SoC/IP designs within our new hardware engineering organization, ensuring high-quality verification processes as we transition from product development to market release.

Responsibilities:

• Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones.
• Author and review verification plans mapping specifications to features, stimulus strategies, coverage goals, and sign-off criteria.
• Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors.
• Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases.
• Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning.
• Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs.
• Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions.
• Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams.
• Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases.
• Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects.
• Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines.
• Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments.
• Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams.
• Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews.
• Represent verification readiness in tapeout sign-off reviews and program-level decisions.
• Support running gate-level simulations as part of design signoff.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Qualifications:

• Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.

Skills:

• Deep expertise in UVM-based testbench architecture and constrained-random verification methodology.
• Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
• Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
• Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
• Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, etc.