Jobs Archive

Principal Physical Design Engineer

Overview: Astera Labs is a leading provider of rack-scale AI infrastructure through innovative connectivity solutions, collaborating with hyperscalers and ecosystem partners to enhance modern AI capabilities. The company’s Intelligent Connectivity Platform integrates various semiconductor technologies with its COSMOS software suite, offering tailored architectures for diverse infrastructure needs. The Principal Physical Design Engineer will be pivotal in designing connectivity ASICs for major cloud service providers and OEMs, overseeing the entire design process from RTL to GDS.

Senior Staff Application Engineer

Overview: Renesas Performance Computing is seeking a skilled individual to join its Power Application Engineering team, focusing on advanced digital power management solutions. The role involves contributing to the development of industry-leading power management ICs, requiring a deep technical understanding of multiphase VR systems and collaboration across functional groups. The successful candidate will play a key role in product definition, business planning, and technical marketing, ensuring alignment with customer needs and market trends.

Design Engineer [Low Power]

Overview: Qualcomm Atheros, Inc. is seeking an experienced ASIC Design Engineer to join its Integrated Wireless Technology team. The role focuses on developing low power micro-architecture and design for WiFi technology, SOC design, and power reduction techniques. The candidate will be involved in the full ASIC development process, from specification to post-silicon bring-up, and will work closely with the verification team.

RTL / Design Verification Engineer

Overview: At AMD, we are dedicated to building innovative products that enhance next-generation computing experiences across various sectors, including AI, data centers, PCs, and gaming. Our culture emphasizes collaboration, bold ideas, and a commitment to excellence, making us a leader in technological advancement. We invite you to join us in shaping the future of AI and beyond while advancing your career in a dynamic environment.

SoC/FPGA Engineer 2

Overview: Nokia in Westford, MA is looking for a skilled engineer specializing in Complex Programmable Logic Device (CPLD) and Field Programmable Gate Array (FPGA) design to enhance its scalable IP routing solutions across various network types. The successful candidate will work within a diverse team to implement high-availability IP routing products.

CAD Engineer

Overview:

{“overview”:”We are seeking an experienced CAD Engineer to develop in-house CAD tools and automate design and verification flows for analog and digital IC design. The ideal candidate will collaborate with various teams to optimize EDA license usage and drive innovation in CAD methodologies. This role also involves mentoring junior engineers and participating in design reviews to enhance design processes.”,”responsibilities”:[“Develop in-house CAD tools for analog design, layout, database management, and SoC sign-off.”,”Automate design and verification flows using languages such as TCL, SKILL, or Python.”,”Collaborate with design engineers, verification engineers, IT, and EDA vendors to optimize EDA license usage.”,”Research and implement advanced CAD methodologies to increase productivity or reduce EDA costs.”,”Mentor junior engineers and foster a culture of continuous learning and professional development.”,”Participate in design reviews, providing constructive feedback to improve design processes and standards.”],”qualifications”:[“Degree in Electrical Engineering or Computer Engineering.”,”10+ years of experience in CAD engineering, with at least 2 years in <28nm technology node EDA methodology.","Strong knowledge of analog design, custom layout, and physical verification flows."],"skills":["Familiarity with common EDA tools (e.g., Synopsys, Cadence, Siemens), including licensing and environment setup.","Experience with SKILL or TCL programming languages.","Proficient in UNIX-based operating systems, file management, and security.","Ability to automate design methodologies and create productivity scripts with design engineers.","Ability to work independently and as part of a team in a startup environment."]}