Overview: Lockheed Martin is seeking an ASIC & FPGA Design Engineer to join their Missiles and Fire Control department in Orlando, FL. This role involves leading the digital development of RF-sensor platforms, creating FPGA-based architectures for defense systems, and collaborating with various teams to ensure high-performance digital solutions for mission-critical applications.
Read MoreOverview: Boeing is seeking multiple Entry Level ASIC/FPGA Design Engineers to join the Electronic Products team in Mountain View, CA. This role involves developing advanced digital ICs and SoCs for critical aerospace and defense programs, fostering a collaborative and inclusive work environment.
Read MoreOverview: Cisco is seeking an ASIC Test Development Engineer for a hybrid role based in San Jose, CA. This position is integral to the ATE test bring-up process, collaborating with various teams to ensure effective testing and production of ASIC units.
Read MoreOverview: Lockheed Martin is seeking an experienced ASIC & FPGA Design Engineer to join their Missiles and Fire Control department. This role involves designing custom analog and mixed-signal ICs for advanced defense systems, with a focus on layout flow from floorplan to tape out.
Read MoreOverview: Hewlett Packard Enterprise (HPE) is seeking an ASIC Design Engineer 2 to join their Juniper Silicon group, focusing on the design of advanced networking chips. This role is primarily onsite and offers a dynamic environment where innovation and teamwork are emphasized. HPE values diverse backgrounds and provides opportunities for personal and professional growth.
Read MoreOverview: Ayar Labs is seeking a Sr. Staff Engineer for ASIC Design to join their innovative team in San Jose. The company specializes in co-packaged optics (CPO) technology, enabling faster and more energy-efficient data transfer for AI applications. The role involves designing, bringing up, and debugging complex digital subsystems within electro-optical digital SoCs, contributing to the advancement of next-generation AI architectures.
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