Overview: General Dynamics Mission Systems (GDMS) is seeking a highly skilled engineer to join our team in Scottsdale, AZ, focusing on ASIC and FPGA development. The ideal candidate will possess a strong background in Electrical or Computer Engineering, with extensive experience in verification processes and tools.
Read MoreOverview: Nvidia is seeking a Senior SOC/IP Methodology Engineer to design and architect next-generation custom SoC/IP solutions. The ideal candidate will have a passion for innovation and a deep understanding of SoC systems, client requirements, and development cycles. This role involves collaboration with internal and external partners to optimize methodologies and ensure high-quality product delivery.
Read MoreOverview: NVIDIA is looking for a motivated and creative Senior Verification Engineer to join the Tegra SoC Memory Subsystem IP verification team. This role involves collaborating with design and architecture teams to implement verification strategies, ensuring functional correctness and performance expectations across various product lines, including consumer graphics, self-driving cars, HPC, cloud computing, and AI.
Read MoreOverview: E-Space is seeking a Verification Engineer to join its innovative team in Saratoga, CA. The company is focused on creating advanced low Earth orbit (LEO) space systems to enhance connectivity and IoT solutions. This role involves designing, simulating, and verifying high-performance integrated circuits for applications like 5G and satellite communications.
Read MoreOverview: NVIDIA is seeking a Senior Infrastructure Engineer to join its CPU SOC HW Infrastructure team, focusing on AI-driven methodologies and tools for chip design and verification. This role offers the chance to impact various product lines, including consumer graphics and self-driving cars, within a dynamic and innovative environment.
Read MoreOverview: NVIDIA is seeking Senior ASIC Timing Design Engineers to join its Networking Silicon engineering team, focusing on the development of high-speed communication devices. This role involves driving physical design and timing for advanced DPUs and SoCs, contributing to innovative chip design in a supportive and diverse environment.
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