Principal ASIC Design Verification Engineer

K2 is a pioneering space startup focused on developing the largest and highest-power satellites for various missions, backed by significant investment and contracts. The company aims to revolutionize satellite technology to support a Kardashev Type II civilization, with multiple launches planned through 2026 and 2027. They are seeking a Principal ASIC Design Verification Engineer to join their innovative team.

Responsibilities:

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Drive advancement of DV methodologies and improvements.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with simulation tools (VCS, Xcelium, Questa), waveform debug tools (Verdi, SimVision), and scripting languages (Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.

Skills:

• Experience with regression management, coverage analysis, and CI/CD automation.
• Experience with developing and integrating reference models.
• Understanding of industry-standard interfaces (APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution.