Principal Physical Design Engineer

Astera Labs is a leading provider of rack-scale AI infrastructure through innovative connectivity solutions, collaborating with hyperscalers and ecosystem partners to enhance modern AI capabilities. The company’s Intelligent Connectivity Platform integrates various semiconductor technologies with its COSMOS software suite, offering tailored architectures for diverse infrastructure needs. The Principal Physical Design Engineer will be pivotal in designing connectivity ASICs for major cloud service providers and OEMs, overseeing the entire design process from RTL to GDS.

Responsibilities:

• Drive PnR activities from RTL to GDS, ensuring robust signoff for complex SoCs or sub-systems.
• Identify and resolve RTL issues in collaboration with the frontend team.
• Utilize custom clocking techniques in design processes.
• Manage high-speed designs involving SERDES and DDR IPs.
• Understand and apply PnR tool and signoff flows, including Extraction, STA, Formality, EM-IR, and DRC/LVS.
• Handle ECO flow using PT DMSA and hyperscale models for larger chips.
• Refine SDC constraints in collaboration with the design team.
• Define and manage I/O timing budgets across hierarchical designs with top-level owners.
• Build hierarchical designs using various models (black-box, ETM, abstract).
• Collaborate with design, implementation, and verification teams to ensure block/top convergence and provide sign-off expertise.

Qualifications:

• Bachelor's in Electrical Engineering or Computer Science; Master's preferred.
• 10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality, and DRC/LVS at both block and full-chip levels.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability in Tcl, Python, or Perl.
• Ability to work independently with strong prioritization and a customer-focused mindset.

Skills:

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience with IP vendors for RTL and hard-macro integration.
• Familiarity with SystemVerilog/Verilog.