Senior ASIC DV Engineer

Join Broadcom as a Verification Engineer, contributing to the development of complex System on Chips (SOCs) for Touch Controllers and Wireless Charging Chips. This role involves architecting verification environments, developing test plans, and collaborating with design engineers to ensure high-quality silicon products.

Responsibilities:

• Architect block and full-chip verification environments using HVLs (UVM) and constrained random techniques.
• Develop test plans and coverage metrics from specifications, writing block and chip-level tests.
• Debug RTL and Gate simulations, collaborating with design engineers to verify fixes.
• Write diagnostics for validation of FPGA prototypes and ASICs.
• Replicate silicon bugs in simulation environments and validate fixes or software workarounds.
• Convert verification tests to test patterns and assist Test Engineers with ATE vector bring-up.
• Evaluate latest verification methodologies and develop scripts to automate verification flows.
• Understand and verify low power silicon for mobile applications, utilizing UPF low power verification flow.
• Translate customer requirements to verify full chip design and architecture.

Qualifications:

• Bachelor's degree with 12+ years of related experience; or
• Master's degree with 10+ years of related experience; or
• PhD with 7+ years of related experience;
• MS or PhD is preferred.

Skills:

• Expertise in mixed-signal simulations (AMS, Spice, etc.).
• Proficient in UVM and constrained random verification techniques.
• Strong debugging skills for RTL and Gate simulations.
• Experience with FPGA and ASIC validation.
• Knowledge of low power verification methodologies and UPF.
• Ability to develop automation scripts for verification flows.