Senior ASIC [Front-End] Design Engineer

Ethernovia, Inc. is at the forefront of developing Ethernet-based networks to enhance the capabilities of software-defined and autonomous vehicles, robotics, and intelligent machines. Founded in 2018, the company has secured $154M in funding from leading technology investors and has been recognized as one of the Top 100 Startups for 2025. Ethernovia is seeking a Senior ASIC Front-End Design Engineer to contribute to the design and development of advanced automotive communication semiconductors.

Responsibilities:

• Lead all aspects of digital SoC design including micro-architecture specification, RTL, verification, synthesis, and static timing analysis.
• Collaborate with system architects, software, hardware, and verification engineers to design and implement advanced automotive communication semiconductors.
• Define product specifications for ASIC's internal and external interactions, data flow, and processing algorithms.
• Work independently with minimal guidance to deliver high-performance custom silicon.

Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field.
• Minimum 10+ years of ASIC RTL design and/or architecture experience.
• Proven track record in developing complex SoCs.
• Strong understanding of digital design fundamentals and methodologies.

Skills:

• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Experience with networking protocols (Ethernet MAC, PHY, TCP/IP, etc.).
• Familiarity with video standards and digital signal processing filters.
• Proficiency in programming languages such as Perl, TCL, C/C++, and Make.