Senior Design Verification Engineer

Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team, focusing on end-to-end verification of critical chassis and interconnect IP blocks. This role emphasizes quality in testbench architecture and collaboration across teams to deliver innovative technology that enhances lives globally.

Responsibilities:

• Own verification planning and execution for key IP features across IP and subsystem integration points.
• Build scalable verification environments and targeted test plans with reusable testbenches, checkers, VIPs, and behavioral models.
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries to unblock progress and maintain execution quality.
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics.
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams.
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows.
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality.

Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Science, or related field with 9+ years of relevant experience OR Master's degree with 6+ years of relevant experience in design verification.
• Extensive background in IP DV with significant experience in subsystem and SoC-level verification.
• Proven expertise in interconnects, caches, and memory subsystems, including bus protocols like AMBA, PCIe, UCIe, and CXL.
• Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features.
• Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation.
• Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems.
• Working familiarity with RTL, physical design, and CAD tool flows.

Skills:

• Excellent communication and organizational skills.
• Ability to adapt as tools, methodologies, and role definitions evolve.
• Hands-on experience with formal verification tools and emulation or FPGA-based verification.
• Track record of delivering reusable, configurable verification collateral.