Senior Director, IO Analog Design Engineering

Intel's Central Engineering Group is seeking a Senior Engineering Leader for the Hard IP and Test Chip Development team, responsible for advancing analog and mixed signal IP for various Intel customers. This role involves shaping the future of IO and chiplet interconnect technology, managing a global team, and ensuring high-quality IP delivery.

Responsibilities:

• Set and refine a multi-generational roadmap for HSIO and D2D IP development.
• Engage with senior architects and executives to define IP landing zones and execution plans.
• Drive IP development across architecture, logic, validation, and analog design teams.
• Manage competing requirements, schedules, and resource balancing across multiple teams.
• Ensure high quality and on-time IP delivery with proactive risk management.
• Lead and develop a high-performing global team of engineers across the US and India.
• Foster a culture of early issue identification and resolution.
• Drive efficiency in the development cycle, including AI solution adoption.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 12+ years of experience.
• Proven experience in analog IP development from concept to launch.
• 10+ years of success in leading silicon teams for complex programs.

Skills:

• Deep knowledge of high-speed serial IO technologies (e.g., PCIe/CXL, USB Type C).
• Expertise in die-to-die technologies (e.g., UCIe).
• Experience managing global, multi-disciplinary engineering organizations.
• Strong negotiation skills with SOC customers.