Senior / Staff Digital Design Engineer

We are looking for experienced Senior/Staff Digital Design Engineers with expertise in CMOS digital design to lead the development of high-speed, real-time data-processing silicon. This role involves end-to-end ownership from algorithm modeling to silicon bring-up, working within a multidisciplinary team focused on next-generation OTPUs that integrate digital, optical, and mixed-signal technologies.

Responsibilities:

• Architect and implement high-throughput digital pipelines in advanced CMOS nodes.
• Prototype and iterate in FPGA, bringing up real-time demos and integrating learnings into ASIC.
• Model algorithms and validate concepts in MATLAB/Simulink, ensuring functional equivalence to gate-level sign-off.
• Own RTL development including synthesis, static-timing closure, and verification.
• Analyze power, performance, and area (PPA) to meet aggressive bandwidth-per-watt targets.
• Collaborate with optical-hardware, mixed-signal, and software teams to optimize interfaces and firmware.
• Mentor junior engineers and lead design reviews.

Qualifications:

• 7+ years of digital design experience for high-performance ASICs or SoCs.
• Proven success in closing timing on high-speed clock domains and integrating high-speed IP.
• Expertise in EDA flows including RTL synthesis and gate-level simulation.
• Demonstrated FPGA prototyping skills and hardware debugging experience.
• Proficiency in MATLAB/Simulink or Python/NumPy for algorithm modeling.

Skills:

• Strong background in electrical engineering and semiconductor physics.
• Excellent communication and collaboration skills.
• Ability to thrive in a fast-paced, ambiguous environment.