SoC Physical Design Engineer

Join Google as a System on a Chip (SoC) Physical Design Engineer, where you'll play a pivotal role in advancing AI/ML hardware acceleration through innovative TPU technology. This position offers the chance to work on cutting-edge silicon solutions that power Google's most demanding applications, contributing to products used by millions worldwide.

Responsibilities:

• Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips.
• Contribute to the design and closure of the subchip and individual blocks from Register-Transfer Level to Graphic Design System.
• Collaborate with RTL/Design and Product Development teams to optimize Power Performance Area (PPA) and conduct feasibility studies for new micro-architectures.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with physical design.
• Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience in block/subchip level PnR for complex SoC.
• Experience with multiple-cycles of SoC in ASIC design.
• Proficiency in scripting languages such as Perl, Python, or Tcl.
• Experience with layout verification and design rules.
• Knowledge of IP integration (e.g., memories, IO’s, and Analog IP) and semiconductor device physics.