Sr Design Verification Engineer – DSP

The ASIC Verification Engineer will be integral in executing a comprehensive test strategy for future ASIC development, focusing on automated regression suites and verification methodologies. This role involves collaboration with design and verification teams to enhance testing processes and frameworks.

Responsibilities:

• Collaborate with design and verification engineers to develop and execute test strategies.
• Write testbenches and test cases based on test plans.
• Develop and improve UVM frameworks.
• Contribute to unit-level and system-level verification deliverables.
• Implement DSP verification environments for testing RTL against MATLAB and Python models.
• Run and automate regression tests.
• Analyze code and functional coverage, providing actionable feedback to teams.
• Prepare and present detailed reports on testing outcomes and verification strategies.

Qualifications:

• BS or MS in Electrical/Computer Engineering or equivalent.
• 10+ years of experience in ASIC verification.

Skills:

• Proficiency in SystemVerilog and UVM for verification.
• Knowledge of verification for DSP algorithms and Mixed Signal systems.
• Familiarity with Cadence Xcelium simulators or similar tools (nice to have).
• Knowledge of scripting languages such as Python or TCL (nice to have).
• Experience working on Linux-based systems (nice to have).