Sr. Staff Engineer, ASIC Physical Design

Ayar Labs is seeking a Sr. Staff Engineer for ASIC Physical Design to join their team in San Jose. The company is at the forefront of AI data solutions, utilizing co-packaged optics to enhance data transfer speeds and efficiency. This role involves the physical design and integration of complex System on Chips (SoCs) that incorporate both digital and photonic components, contributing to the development of high-speed electro-optical engines.

Responsibilities:

• Design physical blocks that integrate digital and custom analog/mixed-signal components.
• Contribute to design for test (DFT) methodologies.
• Develop automated design methodologies for ASIC physical design.
• Execute ASIC physical design tasks including synthesis, place-and-route, static timing analysis (STA), and physical verification (DRC/LVS) for mixed-signal SoCs.
• Coordinate and lead activities among multiple design teams.
• Enhance CAD methodologies to improve design implementation flows.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in ASIC physical design.
• Proven track record of leading successful block implementations with custom IP in advanced process nodes.

Skills:

• Proficient in Verilog RTL.
• Expertise in ASIC synthesis tools (RTL Compiler, Genus, Design Compiler) and place-and-route tools (Encounter, Innovus, ICC).
• Strong knowledge of physical verification processes (DRC, LVS) and static timing analysis.
• Skilled in clock tree synthesis methodologies and customization.
• Experience in designing DFT methodologies (scan insertion, BIST, ATPG).
• Familiarity with ASIC signoff methodologies and requirements.
• Proficient in scripting or programming languages, preferably Python.