Timing Design Engineer

Apple is seeking an ASIC STA Engineer to contribute to the timing aspects of SoC design. This role emphasizes collaboration and innovation, aligning with Apple's commitment to diversity and excellence in product development.

Responsibilities:

• Perform timing sign-off and develop STA and sign-off flows.
• Own IP and block level timing constraints for both regular and custom requirements from synthesis to sign-off.
• Collaborate with RTL designers to understand design intent and clock structure.
• Work with CAD teams to develop and refine timing flows.
• Engage with the Physical Design team to ensure timing closure and sign-off.
• Innovate timing constraints and flows to address timing analysis challenges.

Qualifications:

• BS degree in a technical discipline.
• Minimum 3 years of relevant experience in ASIC design.

Skills:

• Proven knowledge of ASIC timing closure flow and methodology.
• 2+ years of experience in writing ASIC timing constraints and achieving timing closure.
• Expertise in STA tools, particularly Primetime, and understanding of timing corners/modes and process variations.
• Hands-on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages such as Tcl and Perl.
• Familiarity with synthesis, DFT, and backend methodologies and tools.
• Strong communication skills for effective collaboration across diverse teams.