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Choosing an ASIC node is one of the easiest ways to add cost and risk without realizing it.
Many teams assume that the most advanced node automatically delivers the best product. In practice, experienced teams do the opposite: they choose the least aggressive node that still meets the product
Many first-time ASIC conversations fail before they begin.
Not because the idea is wrong, but because expectations are misaligned. Teams approach vendors too early with vague goals, or too late after internal assumptions have already hardened into unrealistic plans.
The result is frustration on both sides: slow quotes,
The question most teams ask is simple:
“At what volume does ASIC become cheaper than FPGA?”
The problem is that the question is usually asked too late, and answered too simplistically. There is no single magic number where ASIC suddenly becomes the obvious choice. The real break-even point
Most ASIC schedules fail quietly.
Not because of one catastrophic mistake, but because they were planned as if silicon behaved like software: linear progress, easy reversals, and unlimited iteration. In reality, ASIC development is constrained by physics, manufacturing, and verification effort. Late changes are expensive, and uncertainty compounds quickly.
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For many teams, the term “ASIC NRE” is enough to stop the conversation.
It sounds like a single, large, opaque number that appears late in the process and instantly kills the business case. In reality, NRE is not one thing, and it is rarely as arbitrary as it feels.
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Most teams don’t decide to move from FPGA to ASIC.
They get pushed there.
At the beginning of a product’s life, FPGA feels like freedom: fast iteration, low upfront cost, and a clear path to demos and early customers. But once a product starts shipping, the rules change.
Integrated circuit (IC) designers are learning that a technique long used on older process nodes is providing even more valuable benefits as they develop devices to be manufactured at advanced technology nodes, including 28nm and beyond. During a period when it takes $10 million or more to bring a device
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The Human Body Model (HBM) Electrostatic Discharge (ESD) test is the oldest and most widely used ESD test in the electronics industry. The JEDEC HBM test isn’t static; it has been revised to keep up with the rapid changes in the semiconductor industry. The latest revision of the spec addresses failures
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Dec. 09, 2025 – The Startup-Nation is increasingly demanding highly efficient, customized classical and post-quantum cryptography. This partnership brings high-assurance system-tailored security to Israel; a “Crypto-Security Boutique.”
Jerusalem, Israel – December 9, 2025 – FortifyIQ, Inc., a provider of high-assurance hardware and software security solutions and services, announced today the signing
This interview with Jens Milnikel, EVP & GM, CMOS Sensors ASICs (CSA) at ams OSRAM, reveals not just the technologies and strategies driving the CSA business of ams OSRAM, but the human stories, partnerships, and vision that set it apart as a true leader in the future of sensing solutions.
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