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Understanding Wafer Bumping Packaging Technology

June 09, 2018, anysilicon

Consumer electronics markets, the mobile phone market in particular, are extremely demanding. They are driven by the desire to pack more and more functionality and enhanced value into the same size handheld device, and often at lower costs. This drive towards smaller, cheaper and thinner consumer electronics has driven the development of highly integrated electronics and stimulated the development of smaller, thinner packages to compliment this advanced technology. This has led to the development of various wafer bumping packaging technologies by leading OSAT companies and semiconductor foundries.

 

The assembly of a die in package has followed an evolutionary trend, which started with wire bonding the chip into a relatively large package and is now moving towards eliminating the package altogether either by Chip On Board (COB) or even embedding the die into the PCB.

 

An important step on this path was to eliminate the wire bonds and replace them with bumps. Wafer Bumping can be considered as a step in wafer processing where solder spheres are attached to the chip I/O pads before the wafer is diced into individual chips. The bumped dies can then be placed into packages or soldered directly to the PCB, i.e. the COB mentioned earlier.

 

The advantages are many; lower inductance, better electrical performance, higher current carrying capacity, a potentially much smaller footprint and lower cost.

 

The bumps are typically placed onto an under bump metallisation (UBM) material that is plated onto the die pads.

 

The bumps are composed of many different materials, defined by the application and use; lead free bumps (SnAg) are common for most applications, though copper pillar bumps offer the advantage of higher density.

 

 

With regards to packaged bumped dies, there are several package types available in the industry today:

 

 

FCBGA – FlipChip Ball Grid Array

 

Ball Grid Array (BGA) flip chip packages are still the most common type of package used with bumped dies; the bumped die is attached (flipped) onto a substrate in the package that routes the signals to the package balls. Advantages are good thermal performance and scalability for physically large and complex dies. Low cost FCBGAs use a laminate (PCB type) substrate; build-up substrates are also available that offer finer pitch routing, enhanced signal and thermal performance, and a lower profile, at a cost. A FCBGA is the preferred flipchip solution for high power designs and designs with a large number of balls (over 100, for example).

WLCSP – Wafer Level Chip Scale Package (Fan In)

 

Wafer Level Chip Scale Package (WLCSP) is truly a chip scale package because it’s essentially a die sized package with bumps that are essentially balls that can be soldered directly to a PCB. There are two main versions; one where balls are attached directly to the die pad openings (this, incidentally, gives the shortest path from die circuit to PCB, so achieves optimum signal performance, lowest inductance, highest speed); and another where a Redistribution Layer (RDL) is used to route the chip pad openings (for example from the edges of the die) to balls that can form a regular array across the die – this is referred to as Fan In. In its final form the WLCSP package is the same size as the die. The RDL may be aluminium (Al), copper (Cu) or a combination of aluminium and copper (AlCu). The back side of the die can be left exposed, plated with metal or some protective layer. This is a preferred solution for low-power, low ball count devices where the small form factor is an advantage,

 

 

eWLB – Embedded Wafer Level BGA (Fan Out)

 

eWLB, or Embedded Wafer Level BGA, is a packaging technology that was introduced in 2009 by ST and STATS ChipPac. It is similar to the WLCSP described above, however the wafers are first diced, the dies spaced apart and a resin material is flowed over the dies then hardened to form a re-constituted wafer. This assembly is referred to as a Fan Out assembly because the relatively small pitch die pads are able to be routed out (fanned out) to a larger pitch array of balls. Multiple RDL levels can be used for complex routing of many pads. The RDL lines are separate by repassivation layers applied in a manner similar to wafer process back-end passivation.

 

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