SignOff Semiconductors

RTL2GDSII expertise with the clear goal of Power, Performance, Area & Schedule

Signoff provides PD design services that are focused on low-power and high-performance designs meant to work on the most advanced technology nodes and processes. Our experienced team comprises of engineers, technology leaders, and managers who are committed to providing reliable design service. Signoff is motivated to ensure that our customer’s product reaches the market much faster.

Designs

• DDR Interfaces and channels.
• High-Speed Graphics
• RISC V Cores
• CPU Cores
• ARM Cores
• 2.5D HBM Design.

High-Speed Clocking

• Top level H/X Trees
• Mesh Structures
• Mult point Clocking.
• Custom Clock Routings.

Tech Nodes

• TSMC: all the way down to 5nm
• GF : 28, 14LPE, 22 FDX
• ST: 28 FDSOI
• Intel : 32, 14, 10
• 55nm Interposer

Methodologies

• Low Power.
• Physical Synthesis
• Latch Arrays.
• Channel/Channel less Top

PD – Low power Implementation

• Multiple Supply voltages

• Power Shutoff
• DVFS
• Clock and power gating
• Voltage islands
• Isolation/level shifters

Power Savings

• Static and Dynamic power reduction
• Multi Vt optimizations
• Clock Power reduction
• Cross talk reduction
• SAIF based PD optimization

PD – DDR and Controller Implementation:

-Lane Skew Matching in the RX for each lane:

• Clock to Data
• Data to Data

-Special Routing on TX and RX Lanes:

• Co-axial Shielding.
• Power ground Shielding.

-Special Signoff:

• Lane skew and data skew
• Setup and Hold
• SSB and DSB

-Custom PnR:

• Custom CTS (TX, FIFO.)
• Long Channels.

RTL – GDSII 

Our team has expertise in all aspects of RTL to GDS II along with Signoff activities and EDA flow and methodology development.

Expertise includes place & route for block build/full chip development with timing closure using industry-standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Drop, EM, Low Power Checks, and Signoff checks.

• Hierarchical/Flat level chip implementation
• Core Hardening or block-level implementations.
• Die Size optimization and related scripting and automation support.
• Physical Verification/DFM support for Hard Macros and full chip level
• Low Power Implementation for Static/Dynamic drop reductions
• Synthesis/Formal equivalence/UPF flow/CLP checks support
• Complete Signoff checks and support.
• Expertise in all industry-standard EDA tools – Synopsys, Mentor, Cadence, Ansys etc.

We have in-depth expertise in Front-end RTL Design and SoC integration for a variety of industry verticals.

Our RTL Design team has an in-depth detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low-power techniques. Our team of experienced design engineers, complemented by a group of mid-level engineers have worked on multiple aspects of the RTL design flow on chips used in the automotive, mobile, networking, multimedia, and processor industries.

Our DFT team has a detailed understanding of the Design for Test requirements and DFT specifications. All aspects of DFT at the block level and at the TOP level are designed and verified using industry-standard tools.

• DFT Planning, Architecture, Flow and Methodology Development.
• DFT Implementation which includes User Defined Registers (UDR) definitions for better controllability, Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
• Automatic Test Pattern Generation (ATPG), ATPG verification.
• DFT simulations for zero delay and timing for SCAN, Boundary SCAN, MBIST & LBIST modes.
• Pre-silicon and Post-silicon Debug.
• ATE Test Program development and Production support.
• ATE Hardware development and packaging.

At Signoff Semiconductors, we have experience in building large maintainable verification environments in both SystemC and SystemVerilog. We can help to preserve your investment in legacy simulation environments or help you to build a new one from starting to inception. The ineffective utilization of newer verification techniques in various verification organizations has led to the following problems:

• Increased use of the license, compute, and storage resources due to sub-optimal constraining of testbench stimulus
• Lack of predictability in verification schedules

Our verification team has been successful at avoiding these problems by not relying purely on a single verification methodology. Based on the complexity of the design-under-test (DUT), we engage one or more of the following methods.

• Directed Test Cases
• Constrained Random Verification using golden reference models.
• Assertion-based verification
• Formal verification to validate “ASIC-style” DUT against a golden reference model.
• Formal verification to validate “ASIC-style” DUT against a golden 

Key Expertise in Design Verification:

• Understanding spec & creating the test plan

• Creating a verification environment using industry-standard methodologies (SV, UVM, OVM), AMBA (AXI*, AHB*), RISCV, SOC/IP, I2C, UART, Mem, VIPs.

• Gate level simulations. Verification closure through corner case verification, coverage closure, and regression closure

Standard Cell:

• High Density, High Speed, Low power
• Design, Layout, and Characterization

Analog & Mixed Signal:

• ADC, DAC, Regulator, PLL, DLL, Transmitter (TX), Receiver (RX)
• High-Speed Serdes, DDR, other PHY Interfaces, USB, Die-to-Die etc

• Memory
• IO Pad Library
• Design & Simulation
• AMS Verification
• Block level, IP level, and Chip level Layout
• Post Layout Extraction (PEX) Simulation & Verification
• Physical Verifications (ANT, DRC, DFM, LVS, ERC, PAD, PERC, ESD/Latch-up, EMIR/SHE etc)

Our expertise covers:

• RTL Design and IP Integration
• Verification
• Pre-Silicon Validation (FPGA Prototype)
• RTL2GDSII (Synthesis, DFT, Place & Route)
• GDSII to Silicon (Tape-out, Foundry and OSAT Interface, Volume Production)

• Process Node Migrations
• FPGA Prototyping
• Migration from FPGA to ASIC

We take complete ownership of the project as well as tools and compute/storage Infra.

Our SOC team brings in the capabilities to provide design services from RTL to Silicon along with FPGA prototyping.

We have Strong relationships with all the leading foundries.

As a Semiconductor Platform Solutions provider,  we provide Silicon-proven platform solutions to  create a solid foundation to provide custom semiconductor solutions in the areas of data converters, SOCs for STB, smart metering, handheld devices, and various IoT applications.