SignOff Semiconductors

USA, India

SignOff Semiconductors is a Spec-to-Silicon SoC/ASIC Design Services company headquartered in Bangalore, India and presence in San Jose CA, providing services for the Automotive, mobile, IoT and communications markets across India and US. Our core expertise includes Physical Design, Verification and Custom Layout across different foundries & nodes (180Nm – 7Nm), along with providing custom silicon solutions using both in-house expertise and third-party IPs. Our team has a cumulative experience 100+ years in Physical Design and taping out 60+ ASICs targeted to leading foundries in various process nodes including 7nm. Over the years we have built expertise on High speed SerDes Ip’s, Graphics Cores, Modems, servers, storage and RISC Cores. We are probably among few companies having nearly zero attrition over the last few years with ranked highest for employee satisfaction.

Services

ASIC Design and System-on-Chip services

Expertise in place & route for block build/full chip development with timing closure using industry standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Drop, EM, Low Power Checks and Signoff checks.

 

  • Hierarchical/Flat level chip implementation
  • Core Hardening or block level implementations.
  • Die Size optimization and related scripting and automation support
  • Physical Verification/DFM support for Hard Macros and full chip level
  • Low Power Implementation for Static/Dynamic drop reductions
  • Synthesis/Formal equivalence/UPF flow/CLP checks support
  • Complete Signoff checks and support.

PD, STA & Synthesis, Flow development

Our team has expertise on all aspects of RTL to GDS II along with Signoff activities and EDA flow and methodology development.

We can undertake all activities of VLSI design with various models ranging from turnkey engagement to ODC and on-site consulting.

Analog and Custom layout Design

We have in house team of experts to work on the Analog mixed signal, custom RF and foundation IP layout. Team has multiple years of experience on designs like Serdes, PLLs, DCOs, OPAMPS, ADCs, DACs, LDO.

 

We can take care of all activities including floorplaning to packaging and full chip activities in the layout.

RTL Design and Verification

We can take ownership of various ASIC and IP designs including but not limited to RISC clusters, ARM clusters, various backbones like AMBA-AXI-AHB, Wishbone etc.

 

We have expert architecture and design engineers who can work closely on the client’s projects from spec to design. We can work one the FPGA prototyping for the customer designs.