Struent Semiconductors

We offer a full spectrum of services, from initial specification to part delivery, including Architecture, Micro-architecture, RTL Design, Verification, DFT, Physical Design, Tape-out, and Packaging. We can provide a complete solution or tailor individual services to meet your specific chip design needs, ensuring flexibility and expertise at every stage.

FPGA prototyping uses reconfigurable chips to create a hardware prototype of a digital design, enabling simulation and testing in real operating conditions at near real-time speeds. This approach emulates the final product’s functionality, allowing extensive testing and optimization before finalizing the design for manufacturing.

Our services help to focus on advanced nodes and cutting-edge chip development, whether you need to port a chip to a newer technology node, modify an existing design, or develop with older technology.

We tailor chip architecture to meet specific automotive needs, including ADAS, infotainment, and power management systems. These chips must comply with stringent safety standards like ISO 26262 for functional safety and AEC-Q100 certification.

• Transformation of traditional monolithic semiconductor design into a more flexible and scalable model.
• Manufacturers can apply the most suitable process technologies for specific functions using Chiplets — like high-performance computing, memory, or I/O.
• Avoids cost and complexity of fabricating an entire monolithic chip on an advanced process node.

It involves integrating the controller module and PHY macro for high-speed IPs like USB, PCIe, Ethernet, or DDR, tailored to specific technology nodes. The process includes synthesis, placement and routing (P&R), static timing analysis (STA), and physical verification (PV) of soft IPs, followed by their integration with the PHY macro. The primary advantage is that the IP is delivered as a single hard macro with finalized timings and integrated I/Os, enabling seamless plug-and-play SoC integration and streamlining overall chip-level integration.