Introduction to LoadBoard Design and Production

August 09, 2012, anysilicon

LoadBoard (LB) is a mandatory, custom made PCB, that acts as a mechanical and electrical interface between the tester (ATE) and the device under test (DUT). LoadBoard has well-defined physical dimensions and it must fit perfectly into the tester.  It is one piece of the entire ASIC Test Solution and it should be specified in the ASIC Test Specification Document. The image shows a Loadboard with a Socket and a Stiffener.

Generally speaking, a LB consists of 2 interfaces: One interface is upwards to the tester’s handler unit. The hander is an automatic pick and place unit that takes the DUT from the tray and place it into the socket. The second interface is downwards to the tester’s pogo pins. These are the tester IO ports that electrically connect the tester to the DUT.


LoadBoard Properties

A properly designed LB is electronically “invisible”, and does not introduce any distortion or delay to the DUT signals. The LoadBoard should be able to support all the tests executed on the tester and be flexible enough to support future testing (for example expanding the test solution to support quad parallel testing).

In fact, many test engineers try to avoid having any active components on the LB but rather have only the necessary passive components to support the ASIC functionality. The trend of simplifying the LoadBoard is coming from need to decrease the probability of failure in production phase that can stop production line. The time of fixing a bug increases when the LoadBoard is complex.

Different testers (ATEs) require different LB size. But they all LoadBoards consist of the same elements:

  1. Socket for the DUT ASIC
  2. Interface pads for the tester
  3. Stiffener  – adding mechanical strength
  4. Some components per DUT requirements (R, C, etc)
  5. Connectors for the debug phase

In some cases, in addition of being an interface board the LB can also contain on board testing capabilities (e.g. such as FPGA). When the tester alone cannot support some specific testing task these could be performed directly on the LB (such as loopbacks).

Design rules for LoadBoard

Almost any layout or PCB engineer can design a LoadBoard, there are no special requirements besides the general understanding of the test and LoadBoard concept. A LB is typically made of RF4 material and normally very thick and consist of 20 layers or more.

LoadBoard design consideration are similar to any other PCB. Power supply distribution, clock signals routing , high speed signals routing, signal integrity, wire length all this design rules applies here too. In some cases, it’s sensible to run some electrical simulation, especially to ensure RF signal performance.

The next phase after layout is successively completed is of course manufacturing/fabrication of the board services and assembly of the board with the various passive or active components and socket.

We always recommend building 2 boards instead of just one because we use the 2nd board as a backup in case there is a failure in the 1st board. These type of failures can stop an entire production line, therefore to lower the risk of delays in production and shipping you may want to consider having a backup LoadBoard. LoadBoard fabrication and assembly could take up to 8-10 weeks depending on the design complexity.


Loadboard is an essential part of the ASIC test solution. Make a robust but yet simple design to ensure minimum production problems, keep one board as a backup if you can afford it.


  • Henrik Rasmussen

    Thank you for a good introduction to test. To improve the article I suggest to add: “A Loadboard (LB) is the interface between the test system and the socket or the probecard. Sockets are used for Component Level Test (CLT) and the probecard is used for Wafer Level Test (WLT). The interface (LB) can contain active circuits to interface to the DUT (either die or component).

    The route is either defined be the application or by the yield vs. the cost. The application can be to test the NVM (Non volatile Memmory) this requires temperature stress which only can be made on wafer level. other wise if the cost for packaging is low and the yield is high the route is preferable (low cost) blind assembly (test after packaging).