IC short circuit failure analysis is the process of determining where an unintended electrical connection exists inside a semiconductor device, package or interconnect structure and identifying the physical defect that created the short.
A short circuit may initially appear only as excessive supply current, unexpectedly low resistance between two nodes, abnormal power consumption or a device that cannot be powered normally. The electrical symptom may be easy to measure while the physical defect responsible for it can be only nanometers or micrometers in size.
The objective of semiconductor short-circuit failure analysis is therefore to progressively narrow the investigation from an electrical symptom to a precise physical location before destructive analysis begins.
Short-circuit analysis may involve:
→ Electrical I-V characterization
→ Resistance measurements
→ Supply-current analysis
→ Thermal fault localization
→ Lock-In Thermography
→ OBIRCH / TIVA
→ Emission Microscopy
→ Magnetic current imaging
→ Nanoprobing
→ EBAC / EBIRCH
→ FIB cross-sectioning
→ SEM / EDS analysis
→ TEM analysis where nanoscale characterization is required
What Is an IC Short Circuit?
An IC short circuit occurs when two electrical structures that should be isolated become unintentionally connected or when an abnormal low-resistance current path develops inside the semiconductor device or package.
The short may exist between structures such as:
→ Power and ground
→ Two metal interconnects
→ Adjacent routing layers
→ Source and drain structures
→ Gate and another transistor terminal
→ Two package traces
→ Bumps or microbumps
→ Solder connections
→ Capacitor electrodes
The resistance of the abnormal path can vary greatly. Some failures appear as extremely low-resistance shorts, while others behave as resistive or non-linear leakage paths.
Symptoms of a Shorted IC
A semiconductor short may be discovered during wafer test, final test, board bring-up, reliability qualification, system operation or field failure analysis.
Typical symptoms include:
→ Abnormally high supply current
→ Low resistance between power and ground
→ Excessive standby current
→ Power supply entering current limit
→ Device heating unexpectedly
→ One power rail collapsing
→ Abnormal I-V behavior
→ Functional failure associated with one supply or circuit block
→ Short between external pins
These symptoms confirm that an abnormal current path may exist, but they do not reveal whether the problem is located in the silicon, package or external interconnect.
Short Circuit vs. Leakage Current
Short circuits and leakage failures can overlap electrically, but they are not always identical.
A very low-resistance connection between two normally isolated conductors is generally treated as a short. A higher-resistance abnormal current path may appear primarily as excessive leakage.
Some defects also exhibit non-linear I-V characteristics, meaning their apparent resistance changes substantially with applied voltage.
Electrical characterization should therefore determine whether the failure behaves as:
→ Very low-resistance short
→ Resistive short
→ Non-linear leakage path
→ Junction-related leakage
→ Voltage-dependent breakdown
This distinction helps determine which fault-localization method is likely to produce the strongest signal.
Typical IC Short-Circuit Failure Analysis Flow
A practical short-circuit investigation can be represented as:
Electrical short reported
↓
Failure reproduced and resistance / I-V characterized
↓
Determine affected pins, rails or nets
↓
Determine whether short is in package, interconnect or die
↓
Choose fault-localization method based on electrical behavior
↓
Localize short to Region of Interest
↓
Correlate location with circuit / layout
↓
Deprocess or cross-section targeted location
↓
SEM / FIB / TEM physical analysis
↓
Failure mechanism identified
↓
Root cause established
Step 1: Verify the Electrical Short
Before physical analysis begins, the reported electrical condition should be reproduced and documented.
Useful measurements can include:
→ Resistance between suspect nodes
→ I-V characteristics
→ Supply current
→ Current at different applied voltages
→ Polarity dependence
→ Temperature dependence
→ Comparison with a known-good device
The electrical behavior helps establish whether the suspected defect is a low-resistance conductive short, resistive path, semiconductor junction failure or another failure mechanism.
Why Controlled Electrical Bias Is Important
Fault-localization techniques frequently require current to flow through the defect.
However, excessive voltage or current can heat the defect, change its resistance or cause additional physical damage. The electrical conditions used during FA should therefore be controlled carefully.
The goal is to produce enough electrical or thermal signal to localize the original failure without significantly altering it before physical analysis.
Step 2: Determine Which Electrical Path Is Shorted
Before attempting microscopic localization, determine which external nodes or internal power domains are involved.
Examples include:
→ VDD to ground
→ One power rail to another power rail
→ I/O pin to supply
→ I/O pin to ground
→ Two signal pins
→ Internal analog nodes
The circuit and layout associated with the affected nodes can substantially reduce the potential search area.
Is the Short in the Package or the Silicon?
One of the most important questions in short-circuit failure analysis is whether the abnormal current path is actually inside the IC die.
A short measured at the package pins may originate from:
→ Semiconductor die
→ Die-to-package interconnect
→ Bond wires
→ Bumps or microbumps
→ Package substrate
→ Package vias
→ Redistribution layers
→ Solder structures
Determining this before destructive decapsulation can prevent the actual package defect from being destroyed during preparation.
Thermal Localization of IC Shorts
A current flowing through a resistive defect can generate localized heat. Detecting that heat is one of the most established approaches for locating semiconductor short circuits.
The general concept is:
Electrical bias applied
↓
Current flows through short
↓
Defect dissipates electrical power
↓
Local temperature increases
↓
Thermal imaging identifies hot spot
↓
Hot spot correlated with circuit layout
Thermal localization can be particularly effective for resistive defects that dissipate enough power to create a detectable temperature difference.
Lock-In Thermography for Short-Circuit Localization
Lock-In Thermography (LIT) improves the ability to detect very small periodic temperature changes associated with electrically stimulated defects.
Instead of relying only on the absolute temperature of the sample, electrical stimulation is modulated and the thermal response is synchronized with that modulation.
This can help reveal hot spots that would be difficult to distinguish using ordinary steady-state thermal imaging.
LIT can be useful for:
→ Resistive shorts
→ Leakage paths
→ Buried electrically active defects
→ Power-distribution defects
→ Certain 3D interconnect failures
Why Some Shorts Are Difficult to Detect Thermally
A common assumption is that the lowest-resistance short should create the hottest spot.
This is not necessarily true.
A very low-resistance defect may dissipate relatively little power at the analysis bias, even while carrying significant current.
As a result, an extremely low-resistance short may produce too little localized heat for conventional thermal localization.
In these situations, a technique that measures current flow rather than defect heating may be more effective.
Magnetic Current Imaging for Low-Resistance Shorts
Magnetic current imaging can be especially valuable for low-resistance shorts.
Electrical current creates a magnetic field. Sensitive magnetic sensors can detect this field and reconstruct the current path through a semiconductor device or package.
Unlike thermal techniques, magnetic current imaging does not depend on the defect dissipating large amounts of power.
The principle is:
Current injected through shorted electrical path
↓
Current generates magnetic field
↓
Magnetic field measured above device
↓
Current density reconstructed
↓
Abnormal current path identified
↓
Short location estimated
A major advantage is that initial analysis can sometimes be performed through the intact package, reducing the risk of losing the original defect before localization.
Die vs. Interconnect vs. Package Short Using Magnetic Imaging
Magnetic current imaging can provide more than a simple hot-spot location.
The pattern of current distribution can help determine whether the short is associated with the semiconductor die, die-to-package interconnect or package routing.
For example:
Die short: abnormal current can be observed distributing through the die and concentrating near the defect
Interconnect short: current may concentrate near the interconnect without significant distribution through the die
Package short: abnormal current may remain primarily within package routing
This distinction can be extremely useful before deciding whether to decapsulate, deprocess or cross-section the device.
OBIRCH for Resistive Short Localization
OBIRCH — Optical Beam Induced Resistance Change — is another powerful technique for semiconductor short localization.
A focused laser is scanned across an electrically biased device. The laser locally heats structures beneath the beam.
If the laser heats the location of a resistive short, the resistance of that path changes.
For a conductive short, resistance generally increases with temperature. Semiconductor structures can show the opposite temperature dependence. In either case, the local resistance change modifies the electrical response of the device.
The process is:
IC electrically biased
↓
Laser scanned across die
↓
Laser locally heats potential short site
↓
Resistance changes
↓
Device current or voltage changes
↓
Electrical response mapped to laser position
↓
Short localized
TIVA and Thermally Induced Short Localization
Thermally Induced Voltage Alteration (TIVA) uses localized thermal stimulation with an electrical biasing configuration designed to detect small changes in device behavior.
Like OBIRCH, it can exploit the temperature dependence of a short-circuit resistance to reveal the failure site.
Backside implementation can also be useful when frontside metal layers obstruct access to lower semiconductor structures.
Can EMMI Locate an IC Short?
Emission Microscopy (EMMI) may help when the electrical defect produces photon-generating semiconductor activity.
Photon emission can be associated with mechanisms such as high-field junction behavior, avalanche breakdown and abnormal transistor operation.
However, a purely metallic low-resistance bridge may generate little or no useful photon emission.
EMMI should therefore be selected according to the expected electrical mechanism rather than assuming every short will emit detectable light.
Frontside vs. Backside Short Localization
Modern integrated circuits can contain many layers of metal above the transistor structures.
This metal stack can obstruct optical techniques or complicate interpretation from the front side.
Backside analysis can provide access through the silicon substrate using suitable infrared optical techniques.
Backside localization may involve:
→ Backside EMMI
→ IR-OBIRCH
→ TIVA
→ Thermal imaging
→ Magnetic current imaging
Backside preparation may be required depending on substrate thickness and the spatial resolution needed.
Nanoprobing a Shorted Semiconductor Device
Once fault localization has narrowed the short to a specific circuit region, nanoprobing can provide direct electrical characterization of individual transistors, vias, metal lines or other local structures.
Nanoprobing can help answer questions such as:
→ Which transistor is electrically abnormal?
→ Is a capacitor actually shorted?
→ Is a via electrically connected when it should not be?
→ Which side of an interconnect contains the defect?
→ Does one local node exhibit abnormal leakage?
Direct I-V measurements can confirm suspected shorts before the analyst commits to site-specific destructive analysis.
Nanoprobing a Shorted Capacitor
A suspected internal capacitor short can be verified by exposing electrical connections to both capacitor electrodes and contacting them with separate nanoprobe tips.
An I-V sweep can then determine whether abnormal current flows between the plates.
A nearby known-good capacitor can be characterized under the same conditions for comparison.
The workflow is:
Suspect capacitor identified
↓
Electrical connections exposed
↓
Nanoprobes contact both electrodes
↓
I-V sweep performed
↓
Short confirmed electrically
↓
Physical analysis targeted to capacitor structure
EBAC for Shorted Interconnects
Electron Beam Absorbed Current (EBAC) can be used with SEM nanoprobing to visualize electrically connected routing.
If two nodes that should be electrically isolated appear connected in the EBAC response, the result can support the presence of a short between the routing networks.
EBAC may establish which networks are shorted even when another localization technique is still required to identify the exact bridging point.
EBIRCH for Resistive Bridges
Electron Beam Induced Resistance Change (EBIRCH) applies a related principle using the scanning electron beam to perturb an electrically biased resistance-related defect.
Small changes in current can be detected and synchronized with the electron-beam position to help localize certain resistive bridges.
Using Layout and CAD Data to Localize the Short
Fault-localization results become more valuable when they are correlated with the circuit layout.
The localized position may be compared with:
→ Power-grid routing
→ Signal nets
→ Via arrays
→ Capacitors
→ Standard cells
→ Individual transistors
→ Package routing
This can turn a thermal, optical or magnetic fault-localization spot into a specific hypothesis about which physical structures are unintentionally connected.
When Should Physical Analysis Begin?
A critical FA decision is determining when the failure has been localized sufficiently to begin irreversible material removal.
Cross-sectioning too early can miss the short or destroy the electrical condition before the defect is understood.
Ideally, several pieces of evidence should point toward the same Region of Interest before destructive physical analysis begins.
This may include:
→ Electrical measurements
→ Thermal localization
→ OBIRCH or TIVA result
→ Magnetic current image
→ EMMI result
→ Nanoprobe confirmation
→ CAD correlation
FIB Cross-Sectioning of an IC Short
Once the Region of Interest has been sufficiently localized, Focused Ion Beam milling can expose the suspected defect with high positional precision.
FIB may be used to investigate:
→ Metal-to-metal bridges
→ Via defects
→ Contact defects
→ Interconnect abnormalities
→ Shorted capacitors
→ Localized material defects
The ability to target a small Region of Interest is especially important because the short itself may occupy only a tiny fraction of the total die area.
SEM Analysis After the Short Is Exposed
SEM can provide high-resolution structural imaging after the failure site has been exposed through FIB milling, cross-sectioning or delayering.
SEM may reveal:
→ Conductive bridge
→ Particle
→ Metal deformation
→ Via abnormality
→ Corrosion
→ Residue
→ Cracking
→ Process-related structural anomaly
If suspicious material is present, SEM-EDS may provide additional elemental information.
When TEM Is Needed
Many semiconductor shorts can be physically characterized using FIB and SEM.
TEM becomes useful when the suspected defect is too small or structurally complex to resolve conclusively using those methods alone.
Examples may include:
→ Nanoscale interfacial bridges
→ Very small contact abnormalities
→ Material layers causing unintended conduction
→ Crystal defects associated with electrical behavior
→ Advanced-node transistor structures
FIB can prepare a site-specific TEM lamella directly through the localized short region.
Common Physical Causes of Semiconductor Shorts
The final physical defect can originate from manufacturing, assembly, reliability stress or field operation.
Potential short mechanisms include:
→ Conductive particle bridging two structures
→ Metal bridging
→ Residual conductive material
→ Via or contact abnormality
→ Dielectric breakdown
→ Junction damage
→ Solder bridging
→ Package-interconnect bridging
→ Contamination or corrosion creating an unintended conductive path
→ Electrical overstress damage
The failure analyst must distinguish the physical feature that carries the short current from the underlying event or process condition that originally created it.
Short Localization Techniques Compared
| Technique |
Useful For |
Important Consideration |
| Electrical I-V |
Characterizing resistance and electrical behavior |
Usually does not provide physical location by itself |
| Thermal Imaging / LIT |
Power-dissipating resistive shorts |
Very low-resistance shorts may generate little heat |
| OBIRCH / TIVA |
Thermally sensitive resistive shorts |
Requires the defect to respond electrically to localized heating |
| EMMI |
Short-related semiconductor activity involving photon emission |
Pure metallic bridges may provide little emission |
| Magnetic Current Imaging |
Low-resistance shorts and buried current paths |
Measures current rather than defect temperature |
| Nanoprobing |
Confirming local transistor, interconnect, via or capacitor shorts |
Requires deprocessing and electrical access |
| EBAC / EBIRCH |
Connected routing and certain resistive bridges |
Requires suitable SEM nanoprobe configuration |
| FIB / SEM |
Physical confirmation of localized short |
Destructive; accurate localization should come first |
Choosing the Best Technique for an IC Short
There is no single fault-localization technique that is best for every short circuit.
The correct approach depends on the electrical characteristics of the failure.
| Observed Failure |
Possible FA Direction |
| Low-resistance power short |
Magnetic current imaging can be particularly useful; electrical characterization first |
| Resistive short generating heat |
Thermal imaging / Lock-In Thermography |
| Thermally sensitive resistive bridge |
OBIRCH / TIVA |
| Junction-related abnormal current |
EMMI may provide useful complementary localization |
| Short suspected in package |
Package FA, X-ray, magnetic current imaging or other package-localization methods |
| Short narrowed to transistor / interconnect |
Nanoprobing, EBAC, EBIRCH |
| Physical site already localized |
FIB cross-section followed by SEM / TEM as required |
Why You Should Not Start With FIB
FIB is extremely powerful, but a semiconductor die can contain billions of possible defect locations.
Without electrical fault localization, selecting a random location for FIB cross-sectioning has a low probability of intersecting the actual short.
A stronger process is:
Electrical characterization
↓
Fault localization
↓
Layout correlation
↓
Nanoprobe confirmation if necessary
↓
Site-specific FIB
↓
Physical characterization
This approach improves the probability that destructive analysis actually intersects the defect.
Package Short vs. Die Short
If a short is measured on a packaged IC, package-level failure should remain part of the hypothesis until evidence shows that the defect lies inside the silicon.
Possible package short mechanisms include:
→ Solder bridge
→ Package-substrate metal bridge
→ Conductive contamination
→ Interconnect damage
→ Microbump bridge
→ Corrosion-related conductive path
Non-destructive package analysis before decapsulation can prevent an important package defect from being lost.
IC Power-to-Ground Short Failure Analysis
A short between a power rail and ground is one of the most direct semiconductor short signatures.
The first goal is to establish which power domain is affected and whether the short behaves as a linear resistance or a voltage-dependent semiconductor path.
The investigation may then progress through:
VDD-GND short confirmed
↓
Resistance and I-V characterized
↓
Affected power domain identified
↓
Thermal / magnetic / laser fault localization selected
↓
Current path localized
↓
Layout identifies suspect structures
↓
Nanoprobe or physical analysis confirms failure
Shorts in Advanced Semiconductor Devices
Advanced IC technologies make short localization more difficult because both the device features and the defects become smaller while the number of interconnect layers increases.
Challenges include:
→ Dense multilevel metallization
→ Smaller contacts and vias
→ Three-dimensional transistor architectures
→ More complex power networks
→ Reduced frontside optical access
→ Increasing importance of backside techniques
→ Smaller Region of Interest for physical analysis
These trends make accurate electrical localization and site-specific sample preparation increasingly important.
Shorts in 2.5D and 3D Structures
A measured short in a 2.5D or 3D semiconductor system can involve structures at several physical depths.
The current path may pass through:
→ Package substrate
→ Interposer
→ Microbumps
→ Through-silicon vias
→ Multiple semiconductor dies
Lock-In Thermography can be adapted for three-dimensional hot-spot localization in suitable structures, while magnetic current imaging can help trace buried current paths without depending on thermal output.
Common Mistakes in Short-Circuit Failure Analysis
→ Assuming every high-current failure is the same type of short
→ Applying destructive analysis before localizing the failure
→ Assuming the defect is in the silicon rather than the package
→ Using excessive electrical stress during localization
→ Expecting EMMI to detect a purely metallic low-resistance bridge
→ Expecting thermal imaging to detect every low-resistance short
→ Ignoring circuit-layout information
→ Failing to compare results with a known-good device when useful
→ Cross-sectioning before the Region of Interest is sufficiently narrow
Typical Root-Cause Workflow for an IC Short
Short confirmed electrically
↓
Electrical mechanism characterized
↓
Fault localization technique selected
↓
Short localized to physical region
↓
Location correlated with layout
↓
Local electrical confirmation where needed
↓
FIB exposes suspected defect
↓
SEM / EDS / TEM characterizes physical structure
↓
Physical failure mechanism identified
↓
Mechanism correlated with process or operating history
↓
Root cause established
What Information Should You Send to an IC Failure Analysis Lab?
Good electrical information can help the laboratory select the correct short-localization method before the sample arrives.
Useful information includes:
→ Device type
→ Semiconductor technology if known
→ Package type
→ Which pins or rails are shorted
→ Measured resistance
→ I-V data
→ Supply-current measurements
→ Failure conditions
→ Temperature dependence
→ Whether the failure is stable or intermittent
→ Previous EMMI / OBIRCH / thermal results
→ Layout or schematic information if available
→ Number of failed samples
→ Known-good comparison samples
Frequently Asked Questions About IC Short-Circuit Failure Analysis
How do you locate a short circuit inside an IC?
The short is first electrically characterized and then localized using techniques selected according to its electrical behavior. These can include thermal imaging, Lock-In Thermography, OBIRCH, magnetic current imaging, EMMI and nanoprobing. Physical confirmation can then be performed using FIB, SEM or TEM.
What is the best technique for locating an IC short?
There is no single best technique. A resistive short that dissipates power may be suitable for thermal localization, while an extremely low-resistance short may be better suited to magnetic current imaging. OBIRCH is useful for thermally sensitive resistive defects, and nanoprobing can provide direct electrical characterization after the suspect region has been exposed.
Can a thermal camera find a shorted IC?
A short that dissipates enough localized power may produce a detectable hot spot. More sensitive approaches such as Lock-In Thermography can detect much smaller thermal signals. However, very low-resistance shorts may dissipate too little power for effective thermal localization.
What is the best method for a very low-resistance IC short?
Magnetic current imaging can be particularly useful because it detects the magnetic field generated by current flow and does not require the defect itself to generate substantial heat.
Can OBIRCH find an IC short?
Yes. OBIRCH is particularly useful for resistive short circuits where localized laser heating changes the resistance of the abnormal current path and produces a measurable electrical response.
Can EMMI find a short circuit?
EMMI can help when the short or associated failure produces photon-generating semiconductor activity. A purely metallic low-resistance bridge may not generate useful photon emission, so other localization methods may be preferable.
Can nanoprobing confirm a short?
Yes. Nanoprobes can directly contact exposed transistor terminals, vias, metal lines or capacitor connections and perform local I-V or resistance measurements to confirm which structure is shorted.
Can an IC short actually be inside the package?
Yes. A short measured between package pins can originate in the die, die-to-package interconnect, bumps, bond wires, package substrate, vias or other package structures. Package-level localization should therefore be considered before destructive decapsulation.
Why is FIB used after fault localization?
FIB can expose a very small site-specific Region of Interest. Fault localization performed first greatly increases the probability that the FIB cross-section will intersect the actual physical short.
Does finding the short location determine root cause?
No. Short localization identifies where abnormal current flows. Physical analysis is normally required to determine what structure created the conductive path and why the defect formed.
Need IC Short Circuit Failure Analysis?
If you have a semiconductor device with excessive current, a power-to-ground short, a resistive short or an unexplained low-resistance path, AnySilicon can help connect your requirement with semiconductor failure analysis laboratories.
Typical short-circuit FA requirements may include:
→ IC short-circuit failure analysis
→ Power-to-ground short localization
→ Low-resistance short localization
→ Lock-In Thermography
→ OBIRCH / TIVA
→ EMMI
→ Magnetic current imaging
→ Nanoprobing
→ EBAC / EBIRCH
→ FIB cross-sectioning
→ SEM / EDS
→ TEM analysis
→ Package short-circuit analysis
Provide the device type, package, affected pins or rails, measured resistance, I-V behavior and any analysis already completed. If you do not know which short-localization technique is required, describe the electrical failure and allow the FA provider to recommend the most appropriate sequence.
