Nanoprobing is an advanced electrical characterization and fault-localization technique used in semiconductor failure analysis to directly investigate individual transistors, contacts, vias and interconnect structures inside an integrated circuit.
Instead of relying only on package-level electrical measurements, nanoprobing allows extremely small conductive structures on a deprocessed semiconductor die to be contacted using precisely controlled probe tips.
Typical nanoprobing applications include:
→ Individual transistor characterization
→ Gate, source and drain leakage measurements
→ Contact and via characterization
→ Copper interconnect probing
→ Resistive-open investigation
→ Short-circuit investigation
→ Memory-cell failure analysis
→ EBAC and EBIC fault localization
→ Active voltage contrast
→ Selection of the correct location for subsequent FIB or TEM analysis
Nanoprobing is particularly valuable because it can bridge the gap between electrical fault localization and destructive physical analysis. Instead of immediately cross-sectioning a suspected region, the failure analyst can electrically characterize individual structures and use the results to determine exactly where the physical investigation should continue.
What Is Semiconductor Nanoprobing?
Semiconductor nanoprobing uses extremely small, precisely positioned electrical probe tips to contact structures inside an integrated circuit after the required device layers have been exposed.
Multiple probes can be positioned independently so that individual transistor terminals, metallization nodes, contacts or vias can be electrically characterized.
A simplified nanoprobing process is:
Electrical failure identified
↓
Suspect circuit region localized
↓
Die deprocessed to required layer
↓
Nanoprobes positioned on target structures
↓
Local electrical measurements performed
↓
Defective transistor or interconnect identified
↓
Physical analysis targeted at exact location
The scale of the probes allows structures to be characterized that are far too small for conventional mechanical probing methods.
Why Nanoprobing Became Important in Semiconductor FA
As semiconductor technologies evolved, integrated circuits incorporated increasing numbers of metal layers, smaller contacts, copper interconnects and low-k dielectric materials.
Traditional approaches that relied on constructing relatively large probe pads using FIB became increasingly difficult as the structures became smaller and the material systems became more complex.
Nanoprobe systems addressed this problem by allowing very small exposed device structures to be contacted directly.
This enables electrical measurements at locations such as:
→ Transistor contacts
→ Individual metal lines
→ Vias
→ Capacitor connections
→ Memory-cell structures
→ Local interconnect nodes
Types of Nanoprobe Systems
Semiconductor nanoprobing can be performed using different tool architectures.
Two important approaches are atomic-force-based nanoprobe systems and nanoprobe systems integrated into a scanning electron microscope.
Atomic-Force-Based Nanoprobing
An atomic-force-based nanoprober uses multiple independently controlled scanning probe tips that can image the sample surface and electrically contact selected device structures.
The probes can be positioned on exposed transistor contacts or metallization nodes for electrical characterization.
SEM Nanoprobing
A SEM nanoprobe places multiple precision probe tips inside the scanning electron microscope chamber.
The SEM image provides high-resolution navigation while the probes make electrical contact with the structures of interest.
SEM-based nanoprobing can also support electron-beam-related techniques such as:
→ Electron Beam Absorbed Current (EBAC)
→ Electron Beam Induced Current (EBIC)
→ Electron Beam Induced Resistance Change (EBIRCH)
→ Active Voltage Contrast
Sample Preparation for Nanoprobing
Sample preparation is one of the most important factors determining whether nanoprobe analysis will succeed.
In many analyses, the semiconductor die must first be removed from the package and mechanically deprocessed until the required device layer is exposed.
For transistor characterization, the target is commonly the contact level below the first metal layer. For metallization analysis, deprocessing proceeds to the metal level that needs to be probed.
Two critical sample-preparation goals are:
→ Good surface planarity
→ Clean conductive surfaces
Both conditions are essential for reliable electrical contact between the nanoprobe tip and the semiconductor structure.
Why Planarity Matters
A semiconductor die may contain several suspect failure locations distributed across a large area.
If deprocessing is not sufficiently planar, one region may reach the required layer while another region remains covered by one or more additional layers.
This can prevent simultaneous nanoprobe analysis of multiple suspected failures.
Poor planarity may also force the analyst to continue removing material, potentially consuming an already exposed defect before it can be physically analyzed.
Good planarity therefore preserves more potential failure sites and increases the probability of ultimately identifying the failure mechanism.
Why Surface Cleanliness Matters
A nanoprobe must establish electrical conduction to extremely small tungsten contacts, copper interconnects or other conductive structures.
Electrical contact can be degraded by:
→ Surface oxidation
→ Non-conductive residue
→ Embedded polishing particles
→ Surface contamination
→ Dirty or oxidized nanoprobe tips
Even if the underlying device is electrically functional, contamination between the probe tip and the contact can make the measurement unreliable or impossible.
The analyst must therefore distinguish between true device resistance and resistance introduced by poor probe contact.
Nanoprobe Tip Condition
The condition of the nanoprobe needles is just as important as the condition of the sample.
Probe tips can become:
→ Worn
→ Bent
→ Oxidized
→ Contaminated with particles
A damaged or contaminated probe tip can prevent good electrical contact and create misleading electrical results.
Clean, sharp probe tips and a clean conductive sample surface are therefore both required for reliable nanoprobe characterization.
Transistor Characterization With Nanoprobes
One of the most powerful applications of nanoprobing is the ability to electrically characterize individual transistors inside a failed integrated circuit.
After the device has been deprocessed to the contact level, probes can be positioned on transistor terminals to perform current-voltage measurements.
Because probe-to-contact resistance is not always known precisely, transistor nanoprobe measurements can be partly qualitative. Comparison with a known-good or correlation transistor can therefore be important, especially when the failure is marginal rather than catastrophic.
Nanoprobe transistor analysis commonly uses two complementary approaches:
→ Four-probe transistor characterization
→ Two-probe terminal-to-terminal characterization
Four-Probe Transistor Characterization
Four-probe measurements are primarily used to determine whether a transistor within the failing circuit is electrically abnormal.
Probes are positioned so that the transistor can be biased and its electrical characteristics measured directly.
The resulting measurements can reveal differences in parameters such as:
→ Drain current behavior
→ Gate-voltage response
→ Leakage behavior
→ Turn-on characteristics
→ Abnormal transistor conduction
Comparison with electrically equivalent transistors or known-good structures can help identify which device within the circuit is responsible for the failure.
Two-Probe Transistor Characterization
After a defective transistor has been identified, two-probe measurements can provide additional information about the location and nature of the defect within that transistor.
Important terminal-to-terminal measurements include:
→ Gate to well
→ Gate to source
→ Gate to drain
→ Source to well
→ Drain to well
→ Drain to source with the gate off
These measurements can help distinguish between possible failure mechanisms affecting different transistor interfaces.
What Two-Probe Measurements Can Reveal
Different leakage or conduction paths provide different clues about the physical location of the transistor defect.
The electrical evidence may indicate possible problems involving:
→ Gate dielectric
→ Gate structure
→ Source or drain junctions
→ Substrate or well
→ Threshold-voltage behavior
→ Crystallographic or substrate defects
The purpose is not necessarily to identify the complete root cause electrically. Instead, the nanoprobe measurements help determine which physical structure should be examined next.
Nanoprobing as a Guide to Physical Analysis
One of the greatest benefits of transistor nanoprobing is that it can guide the subsequent destructive analysis.
For example, nanoprobe results may indicate that the next step should be:
→ Cross-sectional TEM
→ Plan-view TEM
→ Sequential FIB cross-sectioning
→ Additional delayering
→ SEM inspection
This makes nanoprobing an important decision-making technique rather than simply another electrical measurement.
The workflow becomes:
Failed circuit identified
↓
Individual transistor characterized
↓
Defective device identified
↓
Terminal-to-terminal leakage measured
↓
Likely defect location determined
↓
Correct physical-analysis technique selected
Nanoprobing Copper Interconnects
Nanoprobes can also be used to characterize copper metallization inside advanced integrated circuits.
After the die has been deprocessed to the required metal level, exposed copper lines or vias can be electrically contacted.
This can help investigate:
→ Opens
→ Resistive opens
→ Shorts
→ Leakage between metal structures
→ Via connectivity
→ Capacitor connections
Probing Copper Vias
Copper vias can be probed directly after the surrounding dielectric has been recessed enough to expose the top of the via.
However, copper is mechanically soft and a small via can be deformed if it is repeatedly probed.
Careful probe placement and minimal mechanical force are therefore important.
If a via is damaged during probing, the measurement may no longer represent the original device and additional sample preparation may be required.
Probing Metal Lines Instead of Vias
Where the circuit layout allows it, exposed metal lines may provide a more robust probing location than individual vias.
Metal lines can offer several practical advantages:
→ Larger landing area for the probe tip
→ Better mechanical support from surrounding dielectric
→ Greater tolerance for repeated probing
The best probing location therefore depends not only on the electrical circuit but also on the physical robustness of the exposed structure.
Nanoprobing Capacitor Structures
Nanoprobing can also be used to electrically characterize capacitor structures inside an integrated circuit.
If conductive connections to both capacitor plates can be exposed, separate probe tips can contact each side and an I-V sweep can be performed.
This can confirm whether a suspected capacitor is shorted or leaking and can be compared with an adjacent known-good structure.
The process may be:
Suspected capacitor identified
↓
Connections to both plates exposed
↓
Nanoprobes landed on both nodes
↓
I-V sweep performed
↓
Leakage or short confirmed electrically
↓
Physical analysis targeted accordingly
Nanoprobing in Memory Failure Analysis
Memory devices are an important nanoprobing application because a memory failure may be electrically localized to a small number of cells or transistors while the actual physical defect remains unknown.
Multiple suspect locations can sometimes be exposed simultaneously when sample planarity is good.
Nanoprobing can then help determine:
→ Which transistor is abnormal
→ Which terminal interface shows leakage
→ Whether the problem lies in a transistor or routing
→ Which failure site should be preserved for physical analysis
Current Contrast Imaging
Some nanoprobe platforms can generate electrical contrast images in addition to performing direct point measurements.
Current contrast techniques can help visualize electrically connected structures and identify changes in circuit connectivity.
These imaging methods can be particularly valuable when the objective is not merely to measure resistance at a point but to understand where a node routes through a complex circuit.
What Is EBAC?
EBAC stands for Electron Beam Absorbed Current.
In SEM-based nanoprobing, the scanning electron beam interacts with conductive structures while a nanoprobe connected to the circuit collects resulting current.
The measured current can be synchronized with the scanning beam position to generate an image of electrically connected routing.
EBAC-based imaging can therefore help:
→ Trace electrical nodes
→ Investigate interconnect continuity
→ Detect some resistive opens
→ Identify shorted routing
→ Compare expected and abnormal connectivity
EBAC Resistive Contrast Imaging
EBAC can be used to generate resistive contrast information from an interconnect network.
The sensitivity to an open depends strongly on the electrical path between the probe and ground.
A single-probe configuration may detect only very high-resistance opens when the current path to ground passes through a very high-impedance structure such as a transistor gate.
Using a second probe can greatly reduce the ground-path resistance and improve sensitivity to lower-resistance defects.
The general principle is:
Nanoprobe contacts routing
↓
Electron beam scans interconnect
↓
Absorbed current travels through routing
↓
Resistance defect changes collected current
↓
Electrical contrast identifies suspect location
Detecting Resistive Opens With Nanoprobe EBAC
Resistive-open detection illustrates why nanoprobe configuration matters.
If the current can only return through an extremely high-resistance circuit path, the defect itself may also need to have extremely high resistance before it creates enough contrast to be detected.
A second nanoprobe positioned on the opposite side of the suspected defect can create a much lower-resistance path and improve defect sensitivity.
This means that failure analysts must understand the equivalent electrical circuit behind the EBAC image rather than interpreting image contrast alone.
Nanoprobing for Shorted Nodes
EBAC resistive contrast imaging can also indicate that two routing nodes are unintentionally connected.
If a nanoprobe is connected to one node and the resulting image shows both that node and another normally isolated node, the result can indicate an electrical short between the two networks.
However, this may identify the existence of the short without directly identifying the exact physical bridge location.
A complementary localization technique may therefore be required to isolate the actual bridging defect.
EBIRCH With SEM Nanoprobing
Electron Beam Induced Resistance Change (EBIRCH) can be used in SEM nanoprobe analysis to help localize certain resistive shorts between conductive nodes.
The scanning electron beam slightly modifies the electrical behavior of a thermally sensitive defective current path.
The resulting change in bias current can be amplified and mapped to the electron-beam position.
A simplified process is:
Defective routing electrically biased
↓
Electron beam scans circuit
↓
Beam perturbs defective conductive path
↓
Bias current changes slightly
↓
Electrical change amplified
↓
Defect location mapped
Nanoprobing and FinFET Failure Localization
Nanoprobe configurations can also be adapted to investigate advanced transistor structures containing multiple parallel conductive elements.
By applying suitable bias conditions with several probe tips, an abnormal current path may be isolated to a smaller part of the transistor structure.
This illustrates an important advantage of nanoprobing: the electrical configuration can often be tailored to the physical architecture of the device being investigated.
What Is EBIC?
EBIC stands for Electron Beam Induced Current.
When the SEM electron beam penetrates sufficiently deeply into semiconductor material, it can generate electron-hole pairs.
Electric fields within semiconductor junctions separate these carriers, producing a measurable current.
EBIC can therefore provide information about:
→ P-n junction locations
→ Junction shape
→ Implant regions
→ Electrically abnormal silicon structures
→ Certain transistor-level defects
Top-Down and Cross-Section EBIC
EBIC can be performed from a top-down surface when the semiconductor has been sufficiently deprocessed.
With suitable sample preparation, EBIC can also be applied to a cross-section.
Cross-sectional EBIC can provide additional information about the vertical position and shape of an electrically abnormal implant or junction region.
A combined investigation may therefore use:
Nanoprobe I-V measurement
↓
Abnormal transistor behavior identified
↓
Top-down EBIC localizes junction anomaly
↓
Cross-section prepared
↓
Cross-sectional EBIC refines physical location
↓
Physical analysis follows
Electron-Beam Energy and Nanoprobe Imaging
Electron-beam accelerating voltage has a major effect on SEM nanoprobe imaging techniques.
If beam energy is too low, electrons may not penetrate deeply enough to reach the target structure.
If beam energy is increased substantially beyond the required penetration depth, the interaction volume becomes larger and spatial localization can become poorer.
The best localization is therefore often obtained using the lowest electron-beam energy that still reaches the defect or semiconductor structure of interest.
The trade-off is:
Lower beam energy: shallower penetration and potentially better localization
Higher beam energy: greater penetration and potentially stronger signal, but a larger interaction volume
Active Voltage Contrast With Nanoprobes
Active Voltage Contrast (AVC) provides another way to visualize electrically connected structures using a SEM nanoprobe system.
A selected circuit node is electrically biased using a nanoprobe. That voltage changes the number of secondary electrons emitted from the connected structures and alters their brightness in the SEM image.
The electrically connected routing can therefore appear with different contrast from surrounding structures.
AVC can help:
→ Trace electrically connected routing
→ Identify circuit nodes
→ Compare routing behavior
→ Investigate high-resistance structures in suitable cases
Unlike some current-detection nanoprobe techniques, active voltage contrast can use the conventional SEM secondary-electron image itself as the output signal.
Nanoprobing vs. Conventional Probe Stations
Conventional probe stations are highly useful for contacting bond pads, wafer pads and other relatively large electrical structures.
Nanoprobing operates at a very different scale.
It is designed to contact structures such as:
→ Individual transistor contacts
→ Fine interconnects
→ Small vias
→ Memory-cell structures
The ability to characterize individual devices rather than only complete IC input and output nodes is what gives nanoprobing its value in advanced failure analysis.
Nanoprobing vs. EMMI
EMMI and nanoprobing are complementary fault-localization techniques.
EMMI
Emission Microscopy can help identify where electrically active semiconductor behavior occurs, particularly for:
→ Junction leakage
→ Breakdown
→ Latch-up
→ Abnormal transistor activity
Nanoprobing
Nanoprobing can then directly characterize selected local structures through:
→ I-V measurements
→ Terminal-to-terminal leakage measurements
→ Interconnect continuity measurements
→ Electron-beam-assisted imaging techniques
A photon-emission site can therefore provide the region, while nanoprobing can help identify which individual electrical structure inside that region is actually abnormal.
Nanoprobing vs. OBIRCH
OBIRCH and nanoprobing can also serve complementary roles.
OBIRCH uses localized laser heating to detect resistance-related electrical changes across a larger device area.
Nanoprobing can subsequently provide direct electrical access to the local interconnect, via or transistor associated with the suspected failure.
A possible sequence is:
Electrical short or leakage detected
↓
OBIRCH localizes general region
↓
Device deprocessed
↓
Nanoprobe contacts suspect structures
↓
Local electrical defect confirmed
↓
FIB / TEM targets physical failure
Nanoprobing vs. FIB
FIB and nanoprobing perform different but highly complementary functions.
Nanoprobing determines which electrical structure is abnormal. FIB can then expose or cross-section that exact structure.
The combination can reduce the risk of performing destructive physical analysis at the wrong location:
Nanoprobe identifies abnormal device
↓
Electrical interface characterized
↓
Physical location selected
↓
FIB cross-section prepared
↓
SEM / TEM characterizes physical defect
Advantages of Nanoprobing
→ Direct electrical characterization of individual transistors
→ Direct access to nanoscale interconnect structures
→ Can investigate contacts and vias
→ Supports transistor I-V characterization
→ Can distinguish different transistor leakage paths
→ Supports memory failure analysis
→ Can investigate resistive opens and shorts
→ SEM nanoprobing can support EBAC, EBIC and EBIRCH
→ Can guide FIB and TEM analysis
→ Increases the probability that destructive analysis targets the actual defect
Limitations of Nanoprobing
Sample Preparation Is Critical
Poor planarity, contamination or incomplete exposure of the required layer can make electrical characterization extremely difficult or impossible.
Electrical Contact Must Be Reliable
Contaminated surfaces, oxidation or poor probe-tip condition can introduce contact resistance that affects the measurement.
Measurements Can Be Partly Qualitative
Probe-to-device contact resistance may not be known precisely, so marginal transistor failures may require comparison with known-good structures.
Deprocessing Is Usually Required
Access to transistor contacts and internal metallization normally requires removal of overlying materials.
Small Structures Can Be Damaged
Copper vias and other nanoscale structures can be mechanically damaged if probe force is excessive.
Beam Conditions Can Influence Analysis
For SEM nanoprobe techniques, electron-beam energy must be selected carefully because penetration depth, signal strength and spatial localization are interdependent.
Nanoprobing Does Not Automatically Reveal Root Cause
Nanoprobing can identify the electrically abnormal structure and provide strong clues about the defect location, but physical analysis is normally still required to identify the actual material or structural failure mechanism.
Common Semiconductor Failures Investigated With Nanoprobing
| Failure / Suspected Defect |
Nanoprobe Application |
| Abnormal transistor |
Four-probe transistor characterization can compare electrical behavior with reference devices |
| Gate-related leakage |
Two-probe gate-to-source, gate-to-drain or gate-to-well measurements can help identify the affected interface |
| Junction abnormality |
Source-to-well and drain-to-well measurements can characterize abnormal conduction |
| Resistive open |
Direct probing and EBAC resistive contrast can investigate interconnect continuity |
| Shorted routing |
EBAC can identify connected nodes; EBIRCH may help localize certain resistive bridges |
| Defective via |
Direct nanoprobe contact can characterize via connectivity or resistance |
| Shorted capacitor |
Two-probe I-V measurement can verify leakage or shorting between capacitor plates |
| Implant or junction defect |
Nanoprobe I-V combined with EBIC can help localize abnormal semiconductor junction behavior |
| Memory-cell failure |
Individual transistors and routing within the failing cell can be electrically characterized |
Typical Nanoprobe Failure Analysis Workflow
1. Verify the Electrical Failure
Reproduce the failure and understand the electrical signature before destructive sample preparation begins.
2. Localize the Suspect Circuit Region
Use electrical diagnosis or another fault-localization technique to reduce the area that must be investigated.
3. Select the Required Device Layer
Determine whether the analysis requires access to:
→ Transistor contacts
→ Specific metal layer
→ Via layer
→ Another electrically accessible structure
4. Deprocess the Device
Remove overlying materials while maintaining sufficient planarity across the Region of Interest.
5. Prepare Clean Conductive Surfaces
Ensure that exposed contacts or metallization can make reliable electrical contact with the nanoprobe tips.
6. Position the Nanoprobe Tips
Carefully land the required number of probes on the target electrical structures.
7. Perform Electrical Characterization
Measurements may include:
→ Transistor I-V characterization
→ Terminal-to-terminal leakage
→ Resistance
→ Continuity
→ Capacitor leakage
8. Compare With Reference Structures
Where appropriate, compare the failing structure with a known-good or electrically equivalent device.
9. Perform Nanoprobe Imaging if Required
Depending on the nanoprobe system, additional localization may use:
→ Current contrast
→ EBAC
→ EBIC
→ EBIRCH
→ Active Voltage Contrast
10. Select the Physical Analysis
Use the electrical results to choose the most appropriate next step:
→ FIB cross-section
→ SEM inspection
→ Plan-view TEM
→ Cross-sectional TEM
→ Additional delayering
The objective is to preserve and physically analyze the structure most likely to contain the actual failure mechanism.
Frequently Asked Questions About Semiconductor Nanoprobing
What is nanoprobing in semiconductor failure analysis?
Nanoprobing is a technique that uses precisely positioned nanoscale electrical probes to characterize individual transistors, contacts, vias and interconnect structures inside a semiconductor device.
What is a semiconductor nanoprober used for?
A semiconductor nanoprober can be used to characterize transistor behavior, measure leakage between device terminals, investigate interconnect continuity, analyze vias and support advanced electrical fault localization.
Can nanoprobing test an individual transistor?
Yes. Direct characterization of individual transistors is one of the major applications of nanoprobing.
What is four-probe transistor characterization?
Four-probe characterization uses multiple contacts to electrically bias and measure an individual transistor, helping determine whether the transistor behaves abnormally compared with reference devices.
What is two-probe transistor characterization?
Two-probe characterization measures electrical behavior between selected transistor terminals, such as gate-to-source or drain-to-well, to provide clues about the location and nature of a transistor defect.
Can nanoprobing detect gate leakage?
Yes. Gate-to-source, gate-to-drain and gate-to-well measurements can help characterize abnormal gate-related leakage paths.
Can a nanoprobe measure interconnect resistance?
Yes. Exposed metallization and vias can be electrically contacted to investigate resistance, continuity, leakage and shorting.
What is EBAC in nanoprobing?
EBAC stands for Electron Beam Absorbed Current. In a SEM nanoprobe system, absorbed electron-beam current can be collected through a probed circuit node and used to image electrically connected routing and investigate interconnect defects.
What is EBIC?
EBIC stands for Electron Beam Induced Current. The electron beam generates carriers in the semiconductor, and internal electric fields separate them to produce a measurable signal that can image junction-related structures.
What is EBIRCH?
EBIRCH stands for Electron Beam Induced Resistance Change. It uses the scanning electron beam to perturb certain resistive current paths and can help localize electrically active bridging defects.
Why is sample preparation important for nanoprobing?
The probes must make reliable contact with very small conductive structures. Poor planarity, oxidation, contamination or incomplete deprocessing can prevent good electrical contact and make nanoprobe analysis unreliable.
Is nanoprobing destructive?
The electrical probing itself does not necessarily destroy the structure, but the device normally requires significant deprocessing to expose internal contacts or metallization. Very small structures can also be damaged if probe force is excessive.
Does nanoprobing determine root cause?
Nanoprobing can identify the electrically abnormal transistor, interface or interconnect and significantly narrow the suspected failure mechanism. Final root-cause determination usually requires physical analysis such as FIB, SEM or TEM.
Nanoprobing as Part of Semiconductor Failure Analysis
The main value of nanoprobing is its ability to move the failure analysis from a general circuit-level problem to a specific electrical structure.
A failing IC may contain millions or billions of individual structures. Even after conventional fault localization identifies a small region, the analyst may still need to determine exactly which transistor, contact or interconnect is electrically abnormal.
Nanoprobing can progressively narrow that investigation:
Semiconductor device fails
↓
Electrical failure characterized
↓
Fault localization identifies circuit region
↓
Device deprocessed
↓
Individual structures nanoprobe tested
↓
Defective transistor or interconnect identified
↓
Specific defect interface determined
↓
FIB / SEM / TEM targets exact location
↓
Physical failure mechanism identified
↓
Root cause established
The technique is therefore especially valuable when the failure analyst needs more electrical information before committing to irreversible physical analysis.
Looking for a Semiconductor Nanoprobing Lab?
If your semiconductor failure requires electrical characterization of individual transistors, contacts, vias, interconnects or memory-cell structures, a failure analysis laboratory with nanoprobing capabilities may be required.
Typical requirements may include:
→ Semiconductor nanoprobing
→ SEM nanoprobing
→ Atomic-force-based nanoprobing
→ Individual transistor characterization
→ Four-probe transistor measurements
→ Two-probe leakage characterization
→ Contact and via probing
→ Copper metallization probing
→ EBAC imaging
→ EBIC imaging
→ EBIRCH analysis
→ Active Voltage Contrast
→ Memory-device nanoprobing
→ Follow-up FIB / SEM / TEM analysis
When requesting nanoprobe analysis, provide information about the semiconductor technology, device type, package or die condition, failure signature, suspected circuit region, previous fault-localization results and the electrical question that needs to be answered.
The appropriate semiconductor failure analysis provider can then be selected according to the required nanoprobe system, transistor-characterization capability, sample-preparation expertise, SEM-based electrical imaging capabilities and follow-up physical-analysis equipment.
