Gate-all-around (GAA) transistors are a newly introduced type of transistor structure: the gate terminal connects with the channel on all sides. Gate-All-Around transistors are a multi-gate field effect transistors type where a silicon nanowire gate moves around the channel by further scaling down FinFET. The Gate-All-Around structure enables a vertical stacking of a planner channel, which improves the effective width of the channel and enhances transistor drive current. It increases performance by reducing the current leakage and power consumption.
Figure 1 (a) planner MOSFET structure and (b) FinFET transistor structure
As shown in Figure 1 (b), in traditional FinFET transistors, the gate is placed only in the vertical Fin. However, in Gate-All-Around, the gate is wrapped around all sides of the channel material, as described in Figure 2. The large footprint of the gate over the channel enables better electrostatic control than FinFET, improved density, reduced the effect of a short channel, and better subthreshold.
GAA channel may use silicon, germanium, III-V semiconductors during fabrication. However, creating a uniform wrap gate and defect free narrow channel is challenging and becoming active research topics.
They are a newly emerging multi-gate FET type transistor that aims to enhance the FinFET technology. The gate of GAA is wrapped through the entire channel as illustrated in Figure 2. It is essential for better electrostatic control, reducing the short-channel effect, and lowering the voltage threshold. The technology also allows scaling down to smaller dimensions than FinFET. However, uniform wrapping of a very thin silicon nanowire over the channel and further size reduction are some of the manufacturing challenges.
Figure 2 Basic structure of Gate-All Around transistor
The following table presents the comparison of Gate-All-Around transistors to the FinFET transistors in terms of structure, channel type, dimensioning, and performance. Table 1 presents the comparison of Gate All Around transistors to the FinFET transistors in terms of structure, channel type, dimensioning, and performance.
Table 1 Comparison of FinFET and Gate all around transistors
The architecture of GAA is designed to overcome the limitation of FinFET technology when the size shrinks. Its gate electrode wrapped around the channel to provide a better electrostatic gate control of current leakage that is essential in scaling down the transistor size as per Moor’s law. The gate touches the thin channel on all sides to control the leakage and mitigate the short-channel effect at smaller dimensions. Thus, GAA architecture enables integrating more transistor channels in the same area to boost device density per chip.
The all-around architecture of GAA gives many advantages over other planner transistor types as it provides a higher drive current. In addition, they have better control of the on and off state with fast switching due to the improved electrostatic behavior over the channel. If the wrap is designed well, it mitigates the short channel effect and improves the steeper subthreshold swing. On top of that, GAA can fit emerging small electronic applications due to its high scalability to a downsize with negligible leakage current and reduced power loss.
These transistors are essential elements of modern electronics as they have various advantages over other transistors. In current semiconductor technologies, low power consumption and scalability of GAA are the two valuable parameters for future processing nodes. They are utilized in CPU and GPU applications since they have fast switching speeds. In addition, GAA transistors may be deployed in data center devices and network equipment. They are crucial in developing A/D or D/A convertors and memory devices.
The channel consists of either a nanowire or nanosheet thin wire made of silicon, germanium, or an III-V compound. A high dielectric layer is deposited around the nanowire/sheet, and a metal gate made from titanium nitride is wrapped around the dielectric material, as shown in the Figure. In GAA, as a multi-gate FET transistor, the source and drain regions are formed from heavily doped portions of silicon nanosheet/wire. The electrostatic field formed all around the channel when the voltage was applied to the gate metal. The field creates a conduction channel between the p-type drain and n-type sources of the GAA transistor. This provides the gate to control the channel using all-around wrapping.
Figure 3: Nanowire channel GAA transistor structure (a) 3D view and (b) Side view
The following table compares the use of nanowires or nanosheets in the GAA structure in terms of channel type, fabrication, effect of parasitic capacitor, and other technical details.
Figure 4. Nanosheet channel GAA transistor structure (a) 3D view and (b) side view
Considering that GAA transistors are a type of field effect transistor consists the channel connecting a source and drain, the conductivity of the channel is controlled by a gate. The channel is either of nanowire or nanosheet made of common semiconductor material usually silicon. The channel is electrically separated from the channel by High-K dielectric material.
When the gate is biased by positive voltage compared to the source, the channel induces conduction by the majority carrier between the n-type source and p-type drain. As the gate has the potential to generate a controlled electric field for the channel by varying the applied voltage, GAA has better control of the flow of current in the channel.
In a GAA transistor, the gate controls the current flow through the channel. The improved interface area between the gate and channel via an all-round structure leads to high electrostatic control. When an external voltage is applied to the gate electrode, a uniform layer of the surrounding gate creates a conduction path. The GAA structure reduces interferences and effectively modulates the carrier through the channel. Moreover, the short-channel effect is significantly suppressed by gate electrostatic control even in smaller sizes, and the lower threshold voltage improves the transistor ON current.
The impact of electrostatic control on the performance of GAA devices is examined below. The first impact is that the devices have a fast switching speed due to better screening of the drain electric field via a steeper subthreshold swing. The low threshold voltage can control the channel to enhance ON current performance and lower power consumption due to electrostatic. The electrostatic control also assisted in mitigating leakage current even at smaller sizes and improving scalability or device density. Moreover, due to the uniform electrostatic control along the whole channel surface, the variability of GAA transistor devices in the variety of parameters is reduced.
In the GAA structure fabrication, nanowires and nanosheets are manufactured in either a bottom-up or top-down approach. The bottom-up approach includes vapor-liquid-solid growth or template-assisted growth methods. The second one is a top-down approach that includes wet chemical etching, plasma-based etching, sidewall image transfer, trimming, and thinning methods. The selection techniques are based on the availability, the desired dimension, and the properties of the specified application.
The other critical steps in GAA fabrications are dielectric and metal-gate deposition. High-k dielectric materials and a metal-gate deposition can follow the use of atomic layer deposition or chemical vapor deposition methods to achieve precise control of thicknesses and uniformity, which are essential for current controlling and setting up desired threshold voltage, respectively. Accurate etching to access source and drain regions, channel doping, multiple-layer stacking, and careful annealing are the next fabrication processes for high-quality GAA transistor production.
Creating good precision at the nanoscale level is the first challenge in the GAA structure. Forming nanosheets and nanowires in a controlled nanoscale is difficult even with lithography tools. The other challenge is defect control in the etching and channel doping process, which highly affects the performance of the devices. Atomic-level consistency to keep uniformity in the dielectric, stacking, and metal-gate layers is challenging. Accurate placement of source-drain junctions and creating contacts require new etching techniques at the nanoscale.
GAA transistors are manufactured by either a top-down or bottom-up approach. The top-down approaches are FinFET extension and sidewall image transfer. The FinFET extension method starts from traditional FinFET and extends on the existing infrastructure by wrapping the metal gate around to form GAA. The sidewall image transfer techniques begin with a substrate to create a nanowire/sheet by depositing a sacrificial layer and etching selectively. After the nanowire/sheet formation, the high-k dielectric material and metal gate are deposited.
In the bottom-up approach, epitaxial growth and template-assisted growth are the two common techniques. The growth of nanowire/sheet directly on the substrate using chemical vapor deposition in epitaxial techniques. Use a porous template to guide the growth of nanowire/sheet in template-assisted growth. After having the nanowire/sheet, the gate dielectric and metal gate around the grown structure are deposited.
The semiconductor materials for the GAA structure are summarized in the following table in terms of their benefits and drawbacks.
The extreme UV lithography techniques are researched for GAA transistors due to their short wavelength. The direct self-assembly techniques are used for direct printing for block assembly of GAA nanolithography methods for nano-imprinting, and helium ion beam writer for ultimate resolution. On the other hand etching techniques are used for GAA structure in the form of dry etching, wet chemical etching, and pattern transfer are commonly utilized.
The electrical characteristics of GAA include the drive current, threshold voltage, subthreshold swing, and the general V-I relation of the transistors. As stated before, the drive current of GAA is higher due to its fully rounded gate creates better electrostatic current and greater channel surface. This makes them fast-switching applications due to their steeper subthreshold swings and less fringing capacitance. GAA has lower and less variable threshold voltage across a wafer.
Figure 5 The transfer function of GAA transistor
The transfer function curve (IDS-VGS) presented in Figure 5 shows that GAA has a steeper subthreshold swing and fast switching. The lower threshold voltage enables a higher on-state current. The output characteristics (IDS versus VDS), Figure 6 illustrate that there is a linear ohmic output at low drain-source voltage (VDS), and at higher VDS there is a higher saturation current (IDS). They have less variation in IDS with increasing VDS at higher levels due to good gate electrostatics shielding.
Figure 6 The output characteristics GAA (IDS versus VDS)
At variable VGS there is a clear demarcation between on/off states with less drain bias dependency that confirms a reduced short-channel effect. The narrow transition width between on/off states indicates less variability properties of GAA.
The threshold voltage of the GAA structure is affected by cross-sectional channel dimensions and changing the gate material. The doping concentration of the channel and other semiconductor crystals and the dielectric shield also affect the threshold voltage. The effect of temperature on GAA transistor threshold voltage is unavoidable, as in other semiconductor types. The following table summarizes the relation between threshold voltage (Vt) to the affected parameters.
Subthreshold swing is a critical parameter in transistor on/off analysis, which measures how the output current (IDS) rises with increasing gate voltage. GAA has a steeper subthreshold swing at room temperature, which means a fast switching capability. This mitigates both dynamic power consumption during switching and leakage power when the GAA transistors are off. Thus, GAA has low power consumption due to its steeper subthreshold swing and promising for low-power applications.
Short channel effects of a transistor are generated by a strong electric field from the drain that accelerates the carriers in the channel that makes lowering the channel barrier and increasing leakage. However, GAA transistors provide a fully rounded gate that reduces such effect by excellent controlling of electrostatic in all directions.
The comparison of the GAA to FinFET transistors in terms of their electrical characteristics is presented in the following table.
The performance and advantage of GAA transistors come from their physical architecture, which increases drive current, improves downscaling, and minimizes the leakage during the off state of the transistor since GAA has high electrostatic control. They have an ideal switching behavior, immunity to any variability, and low power consumption all are key benefits of GAA.
The gate-all-around (GAA) transistors have a higher drive current due to the wrapped gate over the channel. When the surface area between the channel and gate increases the drive current becomes high. This improves the performance of the GAA transistors even at lower voltage since the transistors developed an excellent electrostatic control to boost the ON state current. The better the gate control leads to a steeper subthreshold swing, as shown ION versus VGS curve. It creates a negligible drain-induced barrier lowering and other short channel effect environment to keep ION high even smaller.
GAA has better power-efficient devices due to their negligible leakage current and short channel effect, steered subthreshold performance, and fast ON/OFF switching. The effect of fringing electric field is almost non-existent on the insulated GAA channels, and these devices can operate at lower drain bias voltage (VDD) in a better performance. All these reasons have developed for active and standby power consumption compared to other transistors.
GAA transistors have a promising downsizing since they have near-ideal electrostatic control of the gate and negligible short-channel effect. The GAA transistor also has a better packing density in a vertical stacking of nanowires/sheets. Furthermore, GAA has less statistical fluctuations for gate action across each dimension and is compatible with advanced lithography fabrication techniques illustrating that they have an excellent potential for further miniaturization.
Currently, GAA transistor technologies are utilized in mobile applications, IoT devices, high-performance computers, network equipment, and so on. They improve battery life and enhance speed and gain. In the future, the application of GAA may extend to small-power budget self-driving vehicles, embedded machine learning equipment, edge computing/IoT devices, and medical applications. In addition, AI-guided drones, robots, avionics, and quantum computing devices will apply GAA transistors.
The advantage of GAA transistors is continuing as the main role in future node technologies. Due to GAA’s gate ability to have excellent electrostatic control, they are becoming scalable without performance degradation and mitigated short channel effect. GAA has performance consistency for any dimension fluctuations, and they are a bit fixable for lithography alignment. Compatibility with newly introduced technologies and their ultra-low voltage operation are the key roles of GAA in the advanced technological nodes.
The challenges and research gaps of GAA transistors are related to fabrication, material types, device design, and integration. In the fabrication process, sub-5 nm pattern precision is becoming a challenge, and varieties of lithographic techniques are studied. Creating uniform dielectric on the nanowire channel, etching nanowire without defect, and reducing variability are difficulties in fabrication. In material engineering, researchers have highly investigated higher mobility channel materials to boost performance with scaled dimensions. Design engineers continually optimized better nanowire/sheet dimensions, spacing, and junctions suited for target applications. Circuit integration such as mixing nanowires/sheets in the same circuit is difficult for GAA and requires a vertical interconnection through monolithic 3D techniques.
The following table presents the summary of a comparison of GAA transistors with other types of transistor architecture. A very low power utilization is promised by the two emerging technologies nanowire FET and tunnel FET. However, they have consistency and uniformity issues are still highly challenged.
