Category Archives: Wafer and Foundries

MPW Run: Cost, Schedule & Booking Tool

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TSMC MPW: CyberShuttle, Cost, Schedule & Access

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TSMC and Sony Plan Image Sensor Joint Venture in Japan

girls holding a phone

Sony Semiconductor Solutions and Taiwan Semiconductor Manufacturing Company have signed a non-binding memorandum of understanding to explore a strategic partnership for the development and manufacturing of next-generation CMOS image sensors. Under the proposed structure, the two companies intend to establish a joint venture in Japan, with Sony expected to be

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Full-Service Foundry: accelerate your analog mixed-signal prototyping with the 2026 MPW calendar

wafer

The ams OSRAM 2026 MPW (Multi-Project Wafer) program expands its technology offering with new 180nm options, including the C18 CMOS specialty platform further enriching the MPW portfolio. For mixed-signal designs in mature nodes, this extension delivers strong analog, high-voltage and BCD capabilities tailored to customer needs.
 
The MPW program

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28nm vs 40nm vs 65nm — The Real Cost, Risk, and Power Trade-Off for ASICs

press release wafer

Choosing between 28nm, 40nm, and 65nm is one of the most common — and most underestimated — decisions in ASIC development.
 
These nodes dominate industrial, automotive, consumer, and IoT ASICs, yet teams often choose based on habit or outdated assumptions. In reality, the differences between 28nm, 40nm, and 65nm

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TSMC 22nm vs UMC 22nm vs GF 22FDX — Which Should You Choose?

press release wafer

Choosing a 22nm process node is not just a scaling decision — it is a strategic choice that affects power consumption, cost structure, ecosystem access, and long-term product risk.
 
For many ASIC and SoC teams, 22nm sits at the crossroads between mature nodes (28nm/40nm) and more advanced, higher-risk technologies.

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