Category Archives: Wafer and Foundries

China-Based IC Production to Represent 21.2% of China IC Market in 2026

market

IC Insights’ 112-page May 2Q Update to The McClean Report 2022 is now available for subscribers to download.  It includes a current outlook for the 2022 global economy, detailed market, unit shipment, and ASP forecasts for IC and O-S-D products through 2026, 2021 semiconductor supplier rankings by product type, the 1Q22 top-25 semiconductor

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2016-2022 Semiconductor Wafer Capacity Trends

IC Insights’ February 1Q Update to The McClean Report 2022 includes an overview of IC industry capacity and wafer start trends from 2002 through 2026.  This bulletin provides a brief summary.
 
The volatile nature of the IC industry is reflected by large swings in annual wafer starts.  Over the past five years, for

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Semicondcutor Foundry Sales Forecast 2016-2022

IC Insights’ forecast for the foundry market through 2026 was part of its recently released 1Q Update to the 2022 McClean Report.  The Update also included analyses of the top-25 2021 semiconductor suppliers, semiconductor industry capital spending, IC industry capacity, the automotive IC market, and detailed forecasts for the DRAM, flash, MCU, MPU, and analog

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Silicon Wafer Cost

Wafer cost is a critical component of IC cost calculation. Wafer cost is based on 4 main factors: wafer technology node, e.g. 5nm, 65nm, 130nm, etc. Wafer options/features, e.g. all the options required on top of the plain vanilla, e.g. mim cap, flash, high voltage, etc. Wafer volume, e.g. how

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Introduction to Intel Foundry Services

This is not the first foray for Intel in the foundry services space. Back in 2013, Intel made its first attempt and started offering production of chips for Altera using the 14nm process. Soon after a couple more companies were announced to have partnered with the Intel Custom Foundry division:

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The Ultimate Guide: FDSOI

FDSOI stands for Fully Depleted Silicon on Insulator. FDSOI is a planar process technology that provides an alternative solution to overcome some of the limitations of bulk CMOS technology at reduced silicon geometries and smaller nodes.
 
The FDSOI process has two distinct features. First starting with the substrate, an

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