Belgrade, Serbia – September 19th, 2017 – AFuzion, the safety-critical systems and certification company and HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a joint webinar on DO-254 best practices and verification optimization for avionics hardware
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I’m going to assume that low cost is not the main value proposition of your product: I’ll assume that it addresses an existing or emerging market in a way that could be summarised as “better”. But it will have a manufacturing cost associated with it, which will be determined by
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Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the
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Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FinFET technology in combination with TSMC’s CoWoS® 2.5D silicon interposer technology and HBM2 memory. This full IP subsystem solution includes an HBM2 controller, PHY and
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eASIC® Corporation (@easic), a fabless semiconductor company that delivers custom integrated circuit platform solutions (eASIC Platform), today announced that it has appointed Si-Edge Technology (Si-Edge) as an advanced design center located in Hong Kong and Shenzhen, China.
The eASIC Platform has been deployed in a wide range of applications spanning wired
As this happens, designers are debating how they can approach designs in such a way that they’re not relying on packing yet-more transistors onto a chip to achieve speed increases. One of the biggest innovations in this industry is going to come from a fundamental reapplication of a technology that
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