Higher bus speeds and lower power consumption are design criteria for most modern digital electronic products. Packaging solutions that provide higher bus speeds at reduced power per bit ratios require design techniques that shorten the distance between chips (to reduce drive currents) and use wider data buses (with finer line-space
Read More
This title, borrowed from Bachman Turner Overdrive’s classic 1974 hit is very relevant today if we apply it to the “Internet of Things”. I’ve been reading and using the term “IoT” for a long time, but realized I needed a clear definition. The Internet is full of similar choices but
Read More
Today, VLSI design flow is a very solid and mature process. The overall VLSI design flow and the various steps within the VLSI design flow have proven to be both practical and robust in multi-millions VLSI designs until now.
Each and every step of the VLSI design flow has
COLUMBIA, Md., May 9, 2017 /PRNewswire/ — Rohde & Schwarz America (RSA), a leading supplier of test & measurement equipment, and DA-Integrated, a company that offers advanced production test systems for development, characterization and volume production, have announced today that they have collaborated to develop an on-wafer RFIC production test
Read More
Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today introduced its new UrLib+™ add-on library for the third-party library on UMC 40LP process technology. UrLib+ is a library package, featuring extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, clock tree noise reduction, robust
Read More
65nm, 28nm, 10nm, 7nm… If you follow Intel’s processors or Xilinx’s FPGAs, you have probably heard about the term semiconductor process node. Semiconductor foundries are investing billions of dollars to make the newest technology node available to the market.
Traditionally, the technology (process) node indicated to the transistor’s gate