The TOLL package is a highly efficient space-saving package featuring extremely low Rds(on) and strong thermal performance making it well suited for high current and high voltage applications. It meets an existing JEDEC package outline, is 30% smaller and 50% thinner than a DDPAK package. The TOLL package leads are designed with wettable flanks
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IC Insights’ November Update to the 2018 McClean Report, released later this month, includes a discussion of the forecasted top-25 semiconductor suppliers in 2018 (the top-15 2018 semiconductor suppliers are covered in this research bulletin). The Update also includes a detailed five-year forecast of the IC market by product type (including dollar volume, unit shipments,
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Since the development of the first ASIC, the IC package was a mean to protect the silicon die and to provide means to PCB connectivity. Back then, the IC package was large and introduced various electrical parasitic.
WLCSP package is one of the latest and most impressive invention of
This interview was held with Randy Caplan, CEO at Silicon Creations.
Tell me a bit about your background?
[randy] I’ve actually spent my whole career in integrated circuit design. I started right at the peak of the dot-com era, and followed the advice of the “experts” at the
GLOBALFOUNDRIES today announced the establishment of Avera Semiconductor LLC, a wholly owned subsidiary dedicated to providing custom silicon solutions for a broad range of applications. Avera Semi will leverage deep ties with GF to deliver ASIC offerings on 14/12nm and more mature technologies while providing clients new capabilities and access
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PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will
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